91 results on '"Maneux, Cristell"'
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2. 3D Logic Cells Design and Results Based on Vertical NWFET Technology Including Tied Compact Model
3. InP DHBT Analytical Modeling: Toward THz Transistors
4. Electrothermal modeling of junctionless vertical Si nanowire transistors for 3D logic circuit design
5. (Invited) Strategies for Characterization and Parameter Extraction of Vertical Junction-Less Nanowire FETs Dedicated to Design Technology Co-Optimization
6. Thermal consideration in nanoscale gate-all-around vertical transistors
7. (Invited) Strategies for Characterization and Parameter Extraction of Vertical Junction-Less Nanowire FETs Dedicated to Design Technology Co-Optimization
8. 3D Logic circuit design oriented electrothermal modeling of vertical junctionless nanowire FETs
9. Analysis of an Inverter Logic Cell based on 3D Vertical NanoWire Junction-Less Transistors
10. InP DHBT test structure optimization towards 110 GHz characterization
11. Extraction of small-signal equivalent circuit for de-embedding of 3D vertical nanowire transistor
12. Circuit Design Flow dedicated to 3D vertical nanowire FET
13. A Logic Cell Design and routing Methodology Specific to VNWFET
14. Access Modelling-based De-embedding Method for High-frequency Characterization of Uni-traveling carrier Photodiodes
15. Electro-Thermal Limitations and Device Degradation of SiGe HBTs with Emphasis on Circuit Performance
16. 0.4-μm InP/InGaAs DHBT with a 380-GHz ${f_{T}}$, > 600-GHz $f_{\max}$ and BVCE0 > 4.5 V
17. InP DHBT Characterization up to 500 GHz and Compact Model Validation Towards THz Circuit Design
18. Multiscale Compact Modelling of UTC-Photodiodes Enabling Monolithic Terahertz Communication Systems Design
19. Investigation of 0.18μm CMOS Sensitivity to BTI and HCI Mechanisms under Extreme Thermal Stress Conditions
20. Compact modeling of 3D vertical junctionless gate-all-around silicon nanowire transistors towards 3D logic design
21. Performance prediction of InP/GaAsSb double heterojunction bipolar transistors for THz applications
22. Towards Monolithic Indium Phosphide (InP)-Based Electronic Photonic Technologies for beyond 5G Communication Systems
23. Design of On-Wafer TRL Calibration Kit for InP Technologies Characterization up to 500 GHz
24. 3D Logic Cells Design and Results Based on Vertical NWFET Technology Including Tied Compact Model
25. Compact Modeling of 3D Vertical Junctionless Gate-all-around Silicon Nanowire Transistors
26. Efficient compact modelling of UTC-photodiode towards terahertz communication system design
27. Scalable compact modeling of trap generation near the EB spacer oxide interface in SiGe HBTs
28. Modeling of NPN-SiGe-HBT Electrical Performance Improvement through Employing Si3N4 Strain in the Collector Region
29. A Multiscale TCAD Approach for the Simulation of InP DHBTs and the Extraction of Their Transit Times
30. Measurement based accurate definition of the SOA edges for SiGe HBTs
31. Impact of SiGe HBT hot-carrier degradation on the broadband amplifier output supply current
32. Scalable Modeling of Thermal Impedance in InP DHBTs Targeting Terahertz Applications
33. Physical, small-signal and pulsed thermal impedance characterization of multi-finger SiGe HBTs close to the SOA edges
34. Analysis of a failure mechanism occurring in SiGe HBTs under mixed-mode stress conditions
35. A Compact Formulation for Avalanche Multiplication in SiGe HBTs at High Injection Levels
36. Scalable Compact Modeling of III–V DHBTs: Prospective Figures of Merit Toward Terahertz Operation
37. Multiscaled Simulation Methodology for Neuro-Inspired Circuits Demonstrated with an Organic Memristor
38. Hot-Carrier Degradation in SiGe HBTs: A Physical and Versatile Aging Compact Model
39. A Large-Signal Monolayer Graphene Field-Effect Transistor Compact Model for RF-Circuit Applications
40. 1/f Noise in 3D vertical gate-all-around junction-less silicon nanowire transistors
41. Avalanche compact model featuring SiGe HBTs characteristics up to BVcbo
42. Reliability-Aware Circuit Design Methodology for Beyond-5G Communication Systems
43. Si/SiGe:C and InP/GaAsSb Heterojunction Bipolar Transistors for THz Applications
44. Microscopic Hot-Carrier Degradation Modeling of SiGe HBTs Under Stress Conditions Close to the SOA Limit
45. Low-Frequency Noise in Advanced SiGe:C HBTs—Part II: Correlation and Modeling
46. Low-Frequency Noise in Advanced SiGe:C HBTs—Part I: Analysis
47. An Accurate Physics-Based Compact Model for Dual-Gate Bilayer Graphene FETs
48. Substrate-coupling effect in BiCMOS technology for millimeter wave applications
49. Graphene FET evaluation for RF and mmWave circuit applications
50. Versatile Compact Model for Graphene FET Targeting Reliability-Aware Circuit Design
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