105 results on '"Mendelson, Avi"'
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2. On Threat of Hardware Trojan to Post-Quantum Lattice-Based Schemes: A Key Recovery Attack on SABER and Beyond
3. A RISC-V SoC with Hardware Trojans: Case Study on Trojan-ing the On-Chip Protocol Conversion
4. Enabling Rabies in King Lear
5. Electromigration-Aware Memory Hierarchy Architecture
6. Teaching computing for complex problems in civil engineering and geosciences using big data and machine learning: synergizing four different computing paradigms and four different management domains
7. Research in computing-intensive simulations for nature-oriented civil-engineering and related scientific fields, using machine learning and big data: an overview of open problems
8. Electromigration-Aware Architecture for Modern Microprocessors
9. Energy Efficient High Performance Processors
10. Static Power Modeling for Modern Processor
11. Compiler-Directed Energy Efficiency
12. Power Modeling at High-Performance Computing Processors
13. Dynamic Optimizations for Energy Efficiency
14. Power Management of Modern Processors
15. A Design Flow and Tool for Avoiding Asymmetric Aging
16. Bimodal-Distributed Binarized Neural Networks
17. Adversarial robustness via noise injection in smoothed models
18. Contrast to Divide: Self-Supervised Pre-Training for Learning with Noisy Labels
19. Hardware Transactions in Nonvolatile Memory
20. Loss aware post-training quantization
21. NICE: Noise Injection and Clamping Estimation for Neural Network Quantization
22. Asymmetric Aging Avoidance EDA Tool
23. A survey of algorithmic methods in IC reverse engineering
24. Batch Method for Efficient Resource Sharing in Real-Time Multi-GPU Systems
25. Sandbox Detection Using Hardware Side Channels
26. Asymmetric aging effect on modern microprocessors
27. Foreword to the First Edition
28. Foreword
29. Topic 4: High-Performance Architecture and Compilers
30. Early-Stage Neural Network Hardware Performance Analysis
31. Towards Designing a Secure RISC-V System-on-Chip: ITUS
32. FlexWatts: A Power- and Workload-Aware Hybrid Power Delivery Network for Energy-Efficient Microprocessors
33. Secure Your SoC: Building System-an-Chip Designs for Security
34. Feature Map Transform Coding for Energy-Efficient CNN Inference
35. A Programming Model and Architectural Extensions for Fine-Grain Parallelism
36. Address Prediction
37. PARROT: Power Awareness Through Selective Dynamically Optimized Traces
38. A Metric-Guided Method for Discovering Impactful Features and Architectural Insights for Skylake-Based Processors
39. Recruiting Fault Tolerance Techniques for Microprocessor Security
40. Security and Privacy in the Age of Big Data and Machine Learning
41. UNIQ
42. SoK
43. Secure Speculative Core
44. ITUS: A Secure RISC-V System-on-Chip
45. Tuning Performance via Metrics with Expectations
46. A Comprehensive Evaluation of Power Delivery Schemes for Modern Microprocessors
47. Rack-Scale Capabilities: Fine-Grained Protection for Large-Scale Memories
48. Energy oriented EDF for real-time systems
49. MIA: Metric Importance Analysis for Big Data Workload Characterization
50. Minimum-Weight Link-Disjoint Node-“Somewhat Disjoint” Paths
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