40 results on '"Pae, S."'
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2. Development and Product Reliability Characterization of Advanced High Speed 14nm DDR5 DRAM with On-die ECC
3. Reliability Improvement with Optimized BEOL Process in Advanced DRAM
4. Reliability Characterization of HBM featuring $\text{HK}+\text{MG}$ Logic Chip with Multi-stacked DRAMs
5. Transistor Reliability Characterization for Advanced DRAM with HK+MG & EUV process technology
6. Reliability Characterization for Advanced DRAM using HK/MG + EUV Process Technology
7. Effect of High Temperature on Recovery of Hot Carrier Degradation of scaled nMOSFETs in DRAM
8. A Comprehensive Reliability Characterization of 5G SoC Mobile Platform Featuring 7nm EUV Process Technology
9. Reliability of Industrial grade Embedded-STT-MRAM
10. 1Gbit High Density Embedded STT-MRAM in 28nm FDSOI Technology
11. Reliability of 8Mbit Embedded-STT-MRAM in 28nm FDSOI Technology
12. Modeling of FinFET Self-Heating Effects in multiple FinFET Technology Generations with implication for Transistor and Product Reliability
13. Reliability engineering: Help enable technology scaling
14. Reliability Characterizations for high-performance, low-power 10nm-FinFET technology
15. Considering physical mechanisms and geometry dependencies in 14nm FinFET circuit aging and product validations
16. From WLR to product reliability and qualifications in the 3D transistor era
17. Gate dielectric TDDB characterizations of advanced High-k and metal-gate CMOS logic transistor technology
18. Multicell and blastocyst survival after vitrification: a comparison between solutions from two different commercial sources
19. High performance 32nm logic technology featuring 2nd generation high-k + metal gate transistors
20. Characterization of SILC and its end-of-life reliability assessment on 45NM high-K and metal-gate technology
21. DRAM as source of randomness
22. A 32nm logic technology featuring 2nd-generation high-k + metal-gate transistors, enhanced channel strain and 0.171μm2 SRAM cell size in a 291Mb array
23. Dielectric breakdown in a 45 nm high-k/metal gate process technology
24. BTI reliability of 45 nm high-K + metal-gate process technology
25. Effect of BTI Degradation on Transistor Variability Advanced Semiconductor Technologies
26. A 45nm Logic Technology with High-k+Metal Gate Transistors, Strained Silicon, 9 Cu Interconnect Layers, 193nm Dry Patterning, and 100% Pb-free Packaging
27. Effect of NBTI degradation on transistor variability in advanced technologies
28. Erscheinungsweisen der spezifischen Sprachentwicklungsstörung im Sprachvergleich - sprachübergreifende oder sprachunabhängige Merkmale?
29. Randomizing Functions: Simulation of a Discrete Probability Distribution Using a Source of Unknown Distribution
30. PMOS NBTI-induced circuit mismatch in advanced technologies
31. Strain specific differences in peribronchial mast cell accumulation in BALB/c vs. C57BL/6 murine models of asthma
32. Bronchiolitis obliterans masquerading as severe persistent asthma in two children
33. Prediction of knock onset and the autoignition site in spark-ignition engines
34. Intra- and extracellular calcium modulates stereocilia stiffness on chick cochlear hair cells.
35. A note on the speleo-minerals in South Korea
36. Erratic fluctuations of sram cache vmin at the 90nm process technology node
37. PMOS NBTI-induced circuit mismatch in advanced technologies
38. Random charge effects for PMOS NBTI in ultra-small gate area devices
39. Multiple layers of silicon-on-insulator (MLSOI) islands fabrication process and fully-depleted SOI pMOSFETs
40. New gate oxide wear-out model for accurate device lifetime projections on vertical drain Nmosfet
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