134 results on '"Tsui, Bing-Yue"'
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2. Triple Self-Aligned Split-Gate Architecture for High-Speed Applications of 4H-SiC VDMOSFETs
3. A 4H-SiC Trench MOS Capacitor Structure for Sidewall Oxide Characteristics Measurement
4. Metal Contact on P-Type 4H-SiC With Low Specific Contact Resistance and Micrometer-Scale Contact Area
5. A Study on the Impact of Gamma Rays Irradiation on 4H-SiC CMOSFETs
6. Investigation of Positive Bias Temperature Instability of 4H-SiC MOS Capacitors and Deep Interface States Extraction at 300°C
7. Influence of Post-Ion-Implantation Annealing Temperature on the Characteristics of Gate Oxide on 4H Silicon Carbide
8. Characterization of 4H-SiC PMOSFET with P+ Poly-Si Gate
9. A multi-contact six-terminal cross-bridge Kelvin resistor (CBKR) structure for evaluation of interface uniformity of the Ti-Al alloy/p-type 4H-SiC contact
10. Investigation of Safe Operating Area on 4H-SiC 600V VDMOSFET with TLP and UIS Test Methods
11. Improving Radiation Hardness of 4H-SiC Power Devices by Local-Oxidation of Silicon Carbide (LOCOSiC) Isolation
12. Design and Characterization of the Junction Isolation Structure for Monolithic Integration of Planar CMOS and Vertical Power MOSFET on 4H-SiC up to 300 °C
13. Modeling and Characterization of the Narrow-Width Effect of 4H-SiC MOSFETs With Local Oxidation of SiC Isolation
14. Dual Gate Oxide CMOS Process on 4H-SiC
15. Design, Process, and Characterization of Complementary Metal–Oxide–Semiconductor Circuits and Six-Transistor Static Random-Access Memory in 4H-SiC
16. An Evaluation for Quality Inspection of Epitaxial Layer and Heavily-doped 4H-SiC Substrate by Simple Schottky Barrier Diode and MOS Capacitor
17. Device isolation process for 4H-SiC CMOS ICs
18. Defect Inspection Techniques in SiC
19. A Study on the Isolation Ability of LOCal Oxidation of SiC (LOCOSiC) for 4H-SiC CMOS Process
20. 1100 V, 22.9 mΩcm2 4H-SiC RESURF Lateral Double-Implanted MOSFET With Trench Isolation
21. Time-dependent dielectric breakdown of gate oxide on 4H-SiC with different oxidation processes
22. High Voltage Gain 4H-SIC CMOS Technology Featuring LOCal Oxidation of SiC (LOCOSiC) Isolation and Balanced Gate Dielectric
23. Demonstration of CMOS Integration With High-Voltage Double-Implanted MOS in 4H-SiC
24. Digital Logic and Asynchronous Datapath With Heterogeneous TFET-MOSFET Structure for Ultralow-Energy Electronics
25. Well-behaved Ge n+/p shallow junction achieved by plasma immersion ion implantation
26. Schottky barrier diodes isolated by local oxidation of SiC (LOCOSiC) using pre-amorphization implantation technology
27. Mechanism of Degradation of Ge NMOSFET with Channel Ion Implantation and Its Recovery
28. Time-Dependent Dielectric Breakdown of Gate Oxide on 4H-SiC with Different Oxidation and Isolation Processes
29. Reduction of Contact Resistivity by Nano-Textured Contact
30. Extraction of Ultra-Low Contact Resistivity by End-Resistance Method
31. Well-behaved 4H-SiC PMOSFET with LOCal oxidation of SiC (LOCOSiC) isolation structure and compromised gate oxide for Sub-10V SiC CMOS application
32. Degradation Mechanism of Ge N+-P Shallow Junction With Thin GeSn Surface Layer
33. Photon-Detection-Probability Simulation Method for CMOS Single-Photon Avalanche Diodes
34. Failure Analysis on TiAl Metallization Process for Ohmic Contact on 4H-SiC pMOSFET
35. Thermal Stability of Shallow Ge N+-P Junction with Thin GeSn Top Layer
36. Effect of Ion-Implantation Temperature on Contact Resistance of Metal/n-Type 4H-SiC With Ar Plasma Treatment
37. Effects of Rapid Thermal Annealing on Ar Inductively Coupled Plasma-Treated n-Type 4H-SiC Schottky and Ohmic Contacts
38. Bandgap engineering of Si1−x Ge xepitaxial tunnel layer for tunnel FETs
39. Reduction of Specific Contact Resistance on n-Type Implanted 4H-SiC Through Argon Inductively Coupled Plasma Treatment and Post-Metal Deposition Annealing
40. Effects of vanadium incorporation on the electron schottky barrier height reduction of NiGe/Ge
41. A comprehensive evaluation of the performance of fin-type epitaxial tunnel layer (ETL) tunnel FET
42. Reduced Junction Leakage by Hot Phosphorus Ion Implantation of NiGe-Contacted Germanium n+/p Shallow Junction
43. Strong Fermi-level pinning induced by argon inductively coupled plasma treatment and post-metal deposition annealing on 4H-SiC
44. Characterization of LOCOS Field Oxide on 4H-SiC Formed by Ar Preamorphization Ion Implantation
45. Scaling of gate dielectric on Ge substrate
46. A comprehensive study on the oxidation of 4H-SiC in diluted N2O ambient
47. Trenched 4H-SiC with tapered sidewall formed by Cl2/O2 reactive ion etching
48. Effect of formation temperature on quality of gate dielectric on germanium substrate
49. Re-examination the effects of selenium segregation on the Schottky barrier height reduction of the NiGe/Ge contact
50. Investigation Into Gate-to-Source Capacitance Induced by Highly Efficient Band-to-Band Tunneling in p-Channel Ge Epitaxial Tunnel Layer Tunnel FET
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