39 results on '"Ali Shafiee"'
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2. Limit-sure reachability for small memory policies in POMDPs is NP-complete.
3. An Agent-Based Modeling and Virtual Reality Application Using Distributed Simulation: Case of a COVID-19 Intensive Care Unit.
4. Griffin: Rethinking Sparse Optimization for Deep Learning Architectures.
5. A distributed digital twin implementation of a hemodialysis unit aimed at helping prevent the spread of the Omicron COVID-19 variant.
6. Sparsity-Aware and Re-configurable NPU Architecture for Samsung Flagship Mobile SoC.
7. FORMS: Fine-grained Polarized ReRAM-based In-situ Computation for Mixed-signal DNN Accelerator.
8. TinyADC: Peripheral Circuit-aware Weight Pruning Framework for Mixed-signal DNN Accelerators.
9. A Distributed Simulation Approach to Integrate AnyLogic and Unity for Virtual Reality Applications: Case of COVID-19 Modelling and Training in a Dialysis Unit.
10. Post-training Piecewise Linear Quantization for Deep Neural Networks.
11. MaiT: Leverage Attention Masks for More Efficient Image Transformers.
12. Rethinking Floating Point Overheads for Mixed Precision DNN Accelerators.
13. ρ: Relaxed Hierarchical ORAM.
14. VAULT: Reducing Paging Overheads in SGX with Efficient Integrity Verification Structures.
15. An MLP-aware leakage-free memory controller.
16. Secure DIMM: Moving ORAM Primitives Closer to Memory.
17. FORMS: Fine-grained Polarized ReRAM-based In-situ Computation for Mixed-signal DNN Accelerator.
18. Design Space Exploration of Sparse Accelerators for Deep Neural Networks.
19. Rethinking Floating Point Overheads for Mixed Precision DNN Accelerators.
20. Algorithm/architecture solutions to improve beyond uniform quantization in embedded DNN accelerators.
21. INXS: Bridging the throughput and energy gap for spiking neural networks.
22. Newton: Gravitating Towards the Physical Limits of Crossbar Acceleration.
23. Near-Lossless Post-Training Quantization of Deep Neural Networks via a Piecewise Linear Approximation.
24. A Method to Improve Adaptivity of Odd-Even Routing Algorithm in Mesh NoCs.
25. ISAAC: A Convolutional Neural Network Accelerator with In-Situ Analog Arithmetic in Crossbars.
26. Understanding and alleviating intra-die and intra-DIMM parameter variation in the memory system.
27. Enabling technologies for memory compression: Metadata, mapping, and prediction.
28. CACTI 7: New Tools for Interconnect Exploration in Innovative Off-Chip Memories.
29. Avoiding information leakage in the memory controller with fixed service policies.
30. Memory bandwidth reservation in the cloud to avoid information leakage in the memory controller.
31. MemZip: Exploring unconventional benefits from memory compression.
32. AFRA: A low cost high performance reliable routing for 3D mesh NoCs.
33. Application-aware deadlock-free oblivious routing based on extended turn-model.
34. A morphable phase change memory architecture considering frequent zero values.
35. Newton: Gravitating Towards the Physical Limits of Crossbar Acceleration.
36. Using Partial Tag Comparison in Low-Power Snoop-Based Chip Multiprocessors.
37. Helia: Heterogeneous Interconnect for Low Resolution Cache Access in snoop-based chip multiprocessors.
38. Industrial control system security taxonomic framework with application to a comprehensive incidents survey.
39. Heterogeneous Interconnect for Low-Power Snoop-Based Chip Multiprocessors.
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