25 results on '"Arnaldo Azevedo"'
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2. Scalable Parallel Programming Applied to H.264/AVC Decoding.
3. An Instruction to Accelerate Software Caches.
4. Parallel H.264 Decoding on an Embedded Multicore Processor.
5. Scalability of Macroblock-level Parallelism for H.264 Decoding.
6. An efficient software cache for H.264 motion compensation.
7. Analysis of video filtering on the cell processor.
8. Analyzing Scalability of Deblocking Filter of H.264 via TLP Exploitation in a New Many-Core Architecture.
9. MoCHA: a Bi-Predictive Motion Compensation Hardware for H.264/AVC Decoder Targeting HDTV.
10. FPGA Prototyping Strategy for a H.264/AVC Video Decoder.
11. Motion Compensation Decoder Architecture for H.264/AVC Main Profile Targeting HDTV.
12. FPGA Design of A H.264/AVC Main Profile Decoder for HDTV.
13. When reconfigurable architecture meets network-on-chip.
14. X4CP32: A New Parallel/Reconfigurable General-Purpose Processor.
15. A New Hybrid Parallel/Reconfigurable Architecture: The X4CP32.
16. A reduced memory bandwidth and high throughput HDTV motion compensation decoder for H.264/AVC High 4: 2: 2 profile.
17. Virtual execution platforms for mixed-time-criticality systems: the CompSOC architecture and design flow.
18. A Highly Scalable Parallel Implementation of H.264.
19. A Multidimensional Software Cache for Scratchpad-Based Systems.
20. The SARC Architecture.
21. Evaluación del rendimiento paralelo en el nivel macro bloque del decodificador H.264 en una arquitectura multiprocesador cc-NUMA.
22. Parallel Scalability of Video Decoders.
23. Accelerating a Multiprocessor Reconfigurable Architecture with Pipelined VLIW Units.
24. Memory Hierarchy Targeting Bi-Predictive Motion Compensation for H.264/AVC Decoder.
25. X4CP32: A Coarse Grain General Purpose Reconfigurable Microprocessor.
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