20 results on '"Eugene Koskin"'
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2. Gate-Level Statistical Timing Analysis: Exact Solutions, Approximations and Algorithms.
3. Quantum Theory and Application of Contextual Optimal Transport.
4. An On-Chip Picoampere-Level Leakage Current Sensor for Quantum Processors in 22-nm FD-SOI CMOS.
5. Design of a 1.5 GHz Low jitter DCO Ring in 28 nm CMOS Process.
6. FPGA Validation of Event-Driven ADPLL.
7. Synchronisation in Noisy PLL Networks: Time Domain Model and its Analysis.
8. Electrostatic Control and Entanglement of CMOS Position-Based Qubits.
9. Simulation Methodology for Electron Transfer in CMOS Quantum Dots.
10. Jitter Optimisation in a Generalised All-Digital Phase-Locked Loop Model.
11. All Digital Phase-Locked Loop Networks for Clock Generation and Distribution: Network Stability, Convergence and Performance.
12. Path-Based Statistical Static Timing Analysis for Large Integrated Circuits in a Weak Correlation Approximation.
13. All-Digital Phase-Locked Loop Arrays: Investigation of Synchronisation and Jitter Performance through FPGA Prototyping.
14. Averaging Techniques for the Analysis of Event Driven Models of All Digital PLLs.
15. Semianalytical model for high speed analysis of all-digital PLL clock-generating networks.
16. Generation of a Clocking Signal in Synchronized All-Digital PLL Networks.
17. A Concept of Synchronous ADPLL Networks in Application to Small-Scale Antenna Arrays.
18. Discrete-time modelling and experimental validation of an All-Digital PLL for clock-generating networks.
19. Mode-locking in a network of kuramoto-like oscillators.
20. Discrete-time modelling and experimental validation of an all-digital PLL for clock-generating networks.
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