183 results on '"I. Ismail"'
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2. Placement Optimization and Power Management in a Multiuser Wireless Communication System With Reconfigurable Intelligent Surfaces.
3. RIS-Assisted Integrated Sensing and Communication Systems: Joint Reflection and Beamforming Design.
4. EMI Performance Analysis in IRS-Aided Multi-User Wireless Communication Systems.
5. Optimizing Reconfigurable Intelligent Surface-Assisted Integrated Sensing and Communication Systems.
6. Deep residual architectures and ensemble learning for efficient brain tumour classification.
7. Optimal Input Selection for Recurrent Neural Network in Predictive Maintenance.
8. Clock signal characterization for signal integrity.
9. Two-dimensional models for quantum effects on short channel electrostatics of lightly doped symmetric double-gate MOSFETs.
10. Thermal Resistance Model for Standard CMOS Thermoelectric Generator.
11. Five-level hybrid DC-DC converter with enhanced light-load efficiency.
12. A 0.4V 90nm CMOS subthreshold current conveyor.
13. Design guidelines for soft implementations to embedded NoCs of FPGAs.
14. Cairo University SPARC V2 (CUSPARC V2) processor.
15. Design guidelines for embeded NoCs on FPGAs.
16. Coupling capacitance extraction in through-silicon via (TSV) arrays.
17. A CMOS based operational floating current conveyor.
18. Design and development of controller for Thermoelectric cooler system.
19. A tunable multi-band/multi-standard receiver front-end supporting LTE.
20. Design of adiabatic TSV, SWCNT TSV, and Air-Gap Coaxial TSV.
21. A new digital locking MPPT control for ultra low power energy harvesting systems.
22. Performance evaluation of FinFET-based FPGA cluster under threshold voltage variation.
23. New TSV-Based applications: Resonant inductive coupling, variable inductor, power amplifier, bandpass filter, and antenna.
24. 5-Level buck converter with reduced inductor size suitable for on-chip integration.
25. Targeting multiple conformations of SARS-CoV2 Papain-Like Protease for drug repositioning: An in-silico study.
26. Facilitating SARS CoV-2 RNA-Dependent RNA polymerase (RdRp) drug discovery by the aid of HCV NS5B palm subdomain binders: In silico approaches and benchmarking.
27. Adaptive Multibit Crosstalk-Aware Error Control Coding Scheme for On-Chip Communication.
28. Speeded up robust features for efficient iris recognition.
29. On the use of a programmable front-end for multi-band/multi-standard applications.
30. A novel dimensional analysis method for TSV modeling and analysis in three dimensional integrated circuits.
31. Low-power all-digital manchester-encoding-based high-speed serdes transceiver for on-chip networks.
32. A variation tolerant driving technique for all-digital self-timed 3-level signaling high-speed SerDes transceivers for on-chip networks.
33. A design oriented model for timing jitter/skew of Voltage-to-Time Converter (VTC) circuits.
34. Circuit design techniques for increasing the output power of switched capacitor charge pumps.
35. Highly-linear voltage-to-time converter (VTC) circuit for time-based analog-to-digital converters (T-ADCs).
36. Variability mitigation using correction function technique.
37. Microscale Solar Energy Harvesting for Wireless Sensor Networks based on Exponential Maximum power locking technique.
38. A macro-modeling approach for through silicon via.
39. Statistical Static Timing Analysis of Conditional Asynchronous Circuits Using Model-Based Simulation.
40. TSV-based on-chip inductive coupling communications.
41. Modeling and analysis of through silicon via: Electromagnetic and device simulation approach.
42. Cloud Computing: Architecture for Efficient Provision of Services.
43. InMnAs magnetoresistive spin-diode logic.
44. A closed form expression for TSV-based on-chip spiral inductor.
45. A 5-10GHz low power bang-bang all digital PLL based on programmable digital loop filter.
46. A 16Gbps low power self-timed SerDes transceiver for multi-core communication.
47. Emitter-coupled spin-transistor logic.
48. Modeling the response of Bang-Bang digital PLLs to phase error perturbations.
49. A novel digital loop filter architecture for bang-bang ADPLL.
50. Cloud Computing: Comparison of Various Features.
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