47 results on '"Kee-won Kwon"'
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2. A Highly-Sensitive and Compact Interconnect Delay Monitoring Circuit for 3-Dimensional System Packages.
3. Si Bridge With Chessboard Patterned Interconnect (CPI): Enabling High Density, High Efficiency Heterogeneous Integration.
4. Fast and Efficient Offset Compensation by Noise-Aware Pre-Charge and Operation of DRAM Bit Line Sense Amplifier.
5. A 6.23-bit FG-based Neuromorphic Synaptic Device with Extended Input Range by Linearity Improvement.
6. Dynamic Power Reduction of TCAM Using Selective Precharging of Match Lines.
7. High Linearity Vector Matrix Multiplier using Bootstrapping and Pre-Emphasis Charging of Non-linear Charge-Trap Synaptic Devices.
8. A 35x10 Charge-Trap Synaptic Memory for 57xMatrix Recognition.
9. Architecture-Accuracy Co-optimization of ReRAM-based Low-cost Neural Network Processor.
10. A High Efficiency Variable Stage and Frequency Charge Pump for Wide Range ISPP.
11. Smart Adaptive Refresh for Optimum Refresh Interval Tracking using in-DRAM ECC.
12. Implementation of an On-Chip Learning Neural Network IC Using Highly Linear Charge Trap Device.
13. A 4-GHz Sub-harmonically Injection-Locked Phase-Locked Loop with Self-Calibrated Injection Timing and Pulsewidth.
14. CMOS-Compatible Learning Device for Neuromorphic Synapse Application using Adjustable Hot Carrier Injections.
15. A 16x16 Programmable Anlaog Vector Matrix Multiplier using CMOS compatible Floating gate device.
16. A 4-GHz Sub-Harmonically Injection-Locked Phase-Locked Loop With Self-Calibrated Injection Timing and Pulsewidth.
17. Low Power Search Engine using Non-volatile Memory based TCAM with Priority Encoding and Selective Activation of Search Line and Match Line.
18. Power Efficient and Reliable Nonvolatile TCAM With Hi-PFO and Semi-Complementary Driver.
19. A Study of Read Margin Enhancement for 3T2R Nonvolatile TCAM Using Adaptive Bias Training.
20. A Non-linear Input Converter Inversely Pre-distorted Against Nonlinear Behavior of FG-based Neuromorphic Synaptic Devices.
21. Binary/Ternary Vector Matrix Multiplier with 3T-2R CBRAM Cell.
22. Local NOR and global NAND match-line architecture for high performance CAM.
23. High performance 4T-2R Non-Volatile TCAM with NMOS Booster.
24. Low Power 3T-2R Non-Volatile TCAM Cell with Dual Match-line.
25. A Fast and Reliable Cross-Point Three-State/Cell ReRAM.
26. A digital DLL with 4-cycle lock time and 1/4 NAND-delay accuracy.
27. A 12.5-Gb/s near-GND transceiver for wire-line UHD video interfaces.
28. A tracked oversampling digital data recovery for Low Latency, fast acquisition, and high jitter tolerance.
29. A 3.0 Gb/s clock data recovery circuits based on digital DLL for clock-embedded display interface.
30. A low-power dual-PFD phase-rotating PLL with a PFD controller for 5Gb/s serial links.
31. 0.37mW/Gb/s low power SLVS transmitter for battery powered applications.
32. A low-power two-line inversion method for driving LCD panels.
33. A study on accelerated built-in self test of multi-Gb/s high speed interfaces.
34. A 5.2-Gb/s Low-Swing Voltage-Mode Transmitter With an AC-/DC-Coupled Equalizer and a Voltage Offset Generator.
35. A 6.4-Gb/s Voltage-Mode Near-Ground Receiver With a One-Tap Data and Edge DFE.
36. CMOS Charge Pump With No Reversion Loss and Enhanced Drivability.
37. An 8Gb/s/pin 9.6ns Row-Cycle 288Mb Deca-Data Rate SDRAM with an I/O Error-Detection Scheme.
38. Full chip integration of 3-d cross-point ReRAM with leakage-compensating write driver and disturbance-aware sense amplifier.
39. Power-Efficient Fast Write and Hidden Refresh of ReRAM Using an ADC-Based Sense Amplifier.
40. A Dual Charge Pump for Quiescent Touch Sensor Power Supply.
41. A Digitally Controlled Oscillator With Wide Frequency Range and Low Supply Sensitivity.
42. A Power-Efficient Voltage Upconverter for Embedded EEPROM Application.
43. A low power CMOS compatible embedded EEPROM for passive RFID tag.
44. Charge-transferred presensing, negatively precharged word-line, and temperature-insensitive power-up schemes for low-voltage DRAMs.
45. A 5-Gbit/s CDR circuit with 1.4 mW multi-PFD phase rotating PLL.
46. A fully digital clock and data recovery with fast frequency offset acquisition technique for MIPI LLI applications.
47. An all-digital PLL with supply insensitive digitally controlled oscillator.
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