88 results on '"Mark Zwolinski"'
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2. Mitigating Cache Contention-Based Attacks by Logical Associativity.
3. Using Formal Methods to Evaluate Hardware Reliability in the Presence of Soft Errors.
4. Session details: Session 4A: Testing, Reliability and Fault Tolerance.
5. Using Hardware Performance Counters to Detect Control Hijacking Attacks.
6. Two-Stage Architectures for Resilient Lightweight PUFs.
7. Hardware Implementation of a Low-Power K-Best MIMO Detector Based on a Hybrid Merge Network.
8. A Reliable PUF in a Dual Function SRAM.
9. A Power Efficient Crossbar Arbitration in Multi-NoC for Multicast and Broadcast Traffic.
10. A Machine Learning Attacks Resistant Two Stage Physical Unclonable Functions Design.
11. Cell Flipping with Distributed Refresh for Cache Ageing Minimization.
12. Cost-efficient design for modeling attacks resistant PUFs.
13. Early detection of system-level anomalous behaviour using hardware performance counters.
14. Fault analysis in analog circuits through language manipulation and abstraction.
15. Fault Analysis in Analog Circuits Through Language Manipulation and Abstraction.
16. An ageing-aware digital synthesis approach.
17. A cost-efficient delay-fault monitor.
18. Lightweight obfuscation techniques for modeling attacks resistant PUFs.
19. Hardware performance counters for system reliability monitoring.
20. NBTI aging evaluation of PUF-based differential architectures.
21. Using Iddt current degradation to monitor ageing in CMOS circuits.
22. Overview of PUF-based hardware security solutions for the internet of things.
23. Ageing Impact on a High Speed Voltage Comparator with Hysteresis.
24. NBTI Lifetime Evaluation and Extension in Instruction Caches.
25. Static Aging Analysis Using 3-Dimensional Delay Library.
26. The European Masters in Embedded Computing Systems (EMECS).
27. High accuracy implementation of Adaptive Exponential integrated and fire neuron model.
28. σLBDR: Congestion-aware logic based distributed routing for 2D NoC.
29. A framework for thermal aware reliability estimation in 2D NoC.
30. Conservative behavioural modelling in systemc-AMS.
31. CERI: Cost-Effective Routing Implementation Technique for Network-on-Chip.
32. VLSI implementation of a scalable K-best MIMO detector.
33. Fault tolerant and highly adaptive routing for 2D NoCs.
34. A novel non-minimal turn model for highly adaptive routing in 2D NoCs.
35. A cost-efficient self-checking register architecture for radiation hardened designs.
36. CARM: Congestion Adaptive Routing Method for On Chip Networks.
37. A low-cost radiation hardened flip-flop.
38. Efficient simulation and modelling of non-rectangular NoC topologies.
39. Fault tolerant routing implementation mechanism for irregular 2D mesh NoCs.
40. Network-on-chip: Current issues and challenges.
41. Circuit Transient Analysis Using State Space Equations.
42. A Large Scale Digital Simulation of Spiking Neural Networks (SNN) on Fast SystemC Simulator.
43. SETTOFF: A fault tolerant flip-flop for building Cost-efficient Reliable Systems.
44. Parallelizing TUNAMI-N1 Using GPGPU.
45. Radiation hardening by design: A novel gate level approach.
46. Acceleration of Functional Validation Using GPGPU.
47. Modelling circuit performance variations due to statistical variability: Monte Carlo static timing analysis.
48. Acceleration of packet filtering using gpgpu.
49. Modelling Smart Card Security Protocols in SystemC TLM.
50. Design metrics for RTL level estimation of delay variability due to intradie (random) variations.
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