57 results on '"Rajeev Jain"'
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2. DE-HNN: An effective neural model for Circuit Netlist representation.
3. Less is More: Hop-Wise Graph Attention for Scalable and Generalizable Learning on Circuits.
4. DE-HNN: An effective neural model for Circuit Netlist representation.
5. An Automation Framework for Comparison of Cancer Response Models Across Configurations.
6. Accelerating Flash-X Simulations with Asynchronous I/O.
7. Exascale models of stellar explosions: Quintessential multi-physics simulation.
8. Automated Design of Analog Circuits Using Reinforcement Learning.
9. Framework and Methodology for Verification of a Complex Scientific Simulation Software, Flash-X.
10. Fast and Accurate PPA Modeling with Transfer Learning.
11. From System-on-Chip (SoC) to System on Multi-Chip (SoMC) architectures: Scaling integrated systems beyond the limitations of deep-submicron single chip technologies.
12. Flash-X, a multiphysics simulation software instrument.
13. Efficient reinforcement learning for automating human decision-making in SoC design.
14. Checkpoint/Restart for Lagrangian particle mesh with AMR in community code FLASH-X.
15. Flash-X: A multiphysics simulation software instrument.
16. CANDLE/Supervisor: a workflow framework for machine learning applied to cancer research.
17. Data-driven CAD or Algorithm-Driven CAD: Competitors or Collaborators?
18. Kano integrated robust design approach for aesthetical product design: a case study of a car profile.
19. PostBL: Post-mesh Boundary Layer Mesh Generation Tool.
20. A New Heuristic for Disassembly Line Balancing Problems with AND/OR Precedence Relations.
21. Creating Geometry and Mesh Models for Nuclear Reactor Core Geometries Using a Lattice Hierarchy-Based Approach.
22. Spectrum Sensing Design Framework Based on Cross-Layer Optimization of Detection Efficiency.
23. Using data mining synergies for evaluating criteria at pre-qualification stage of supplier selection.
24. A Kano model, AHP and M-TOPSIS method-based technique for disassembly line balancing under fuzzy environment.
25. A heuristic approach for U-shaped assembly line balancing to improve labor productivity.
26. Creating geometry and mesh models for nuclear reactor core geometries using a lattice hierarchy-based approach.
27. DEFACTO: A Design Environment for Adaptive Computing Technology.
28. Simulation and Synthesis of VLSI Communication Systems.
29. A low power architecture for wireless multimedia systems: lessons learned from building a power hog.
30. Techniques for FPGA Implementation of Video Compression Systems.
31. An Algorithm-Driven Processor Design for Video Compression.
32. An Integrated Technology CAD System for Process and Device Designers.
33. Real Time Implementation of Pruned Tree Search Vector Quantization.
34. Decimation filter compiler for oversampling A/D applications.
35. Architectures and integrated circuits for real time vector quantization of images.
36. Hi-PASS: a computer-aided synthesis system for maximally parallel digital signal processing ASICs.
37. Computer-aided design of high-speed lattice wave digital filter integrated circuits.
38. A functional silicon compiler for high speed FIR digital filters.
39. Adaptive radio for multimedia wireless links.
40. A 110-K transistor 25-MPixels/s configurable image transform processor unit.
41. VLSI in Mobile Communication.
42. On-line broadcast archives for interactive video.
43. An integrated testbed for wireless multimedia computing.
44. Strategies for design automation of high speed digital filters.
45. A single-chip 12.7 Mchips/s digital IF BPSK direct sequence spread-spectrum transceiver in 1.2 μm CMOS.
46. Performance Analysis of an All-Digital BPSK Direct-Sequence Spread-Spectrum IF Receiver Architecture.
47. An integrated circuit design for pruned tree-search vector quantization encoding with an off-chip controller.
48. DDFSGEN.
49. An integrated CAD system for algorithm-specific IC design.
50. FIRGEN: a computer-aided design system for high performance FIR filter integrated circuits.
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