20 results on '"Se-Joong Lee"'
Search Results
2. A reconfigurable crossbar switch with adaptive bandwidth control for networks-on-chip.
3. SILENT: serialized low energy transmission coding for on-chip interconnection networks.
4. On-chip network based embedded core testing.
5. A 10Gbps/port 8×8 shared bus switch with embedded DRAM hierarchical output buffer.
6. A high-speed and lightweight on-chip crossbar switch scheduler for on-chip interconnection networks.
7. A distributed crossbar switch scheduler for on-chip networks.
8. A practical method to use eDRAM in the shared bus packet switch.
9. A 670 ps, 64 bit dynamic low-power adder design.
10. One chip-low power digital-TCXO with sub-ppm accuracy.
11. 81.6 GOPS Object Recognition Processor Based on a Memory-Centric NoC.
12. Low-power network-on-chip for high-performance SoC design.
13. Packet-switched on-chip interconnection network for system-on-chip applications.
14. Analysis and Implementation of Practical, Cost-Effective Networks on Chips.
15. A 120-mW 3-D rendering engine with 6-Mb embedded DRAM and 3.2-GB/s runtime reconfigurable bus for PDA chip.
16. Race logic architecture (RALA): a novel logic concept using the race scheme of input variables.
17. A reconfigurable multilevel parallel texture cache memory with 75-GB/s parallel cache replacement bandwidth.
18. An 80/20-MHz 160-mW multimedia processor integrated with embedded DRAM, MPEG-4 accelerator and 3-D rendering engine for mobile applications.
19. A network-on-chip with 3Gbps/wire serialized on-chip interconnect using adaptive control schemes.
20. Low energy transmission coding for on-chip serial communications.
Catalog
Books, media, physical & digital resources
Discovery Service for Jio Institute Digital Library
For full access to our library's resources, please sign in.