28 results on '"Won Young Lee"'
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2. Design of a Low-Jitter Digitally Controlled Oscillator With Supply Noise Compensation.
3. A 0.6-V 4-MS/s Asynchronous SAR ADC With 2-Bit Conversion/Cycle Time-Domain Comparator.
4. A Study on the Assistive System for Safe Elevator Get on of Wheelchair Users with Upper Limb Disability.
5. A 1.0-V 12-Gb/s Two-FIR Tap DFE with Tap Weighting Adjustable Filters.
6. An Anti-Harmonic-Lock Frequency Detector for Continuous-Rate Clock and Data Recovery.
7. A Single-Ended Transmitter With Low Switching Noise Injection and Quadrature Clock Correction Schemes for DRAM Interface.
8. A Low EMI Transmitter for DRAM Interface with Quadrature Clock Corrector.
9. A Wide Range Digitally Controlled Oscillator with Direct Proportional Loop Control.
10. A 0.6-V 400-KS/s Low Noise Asynchronous SAR ADC With Dual-Domain Comparison.
11. A Fast Locking Duty Cycle Corrector with High Accuracy.
12. A 10-Bit 400-KS/s Low Noise Asynchronous SAR ADC with Dual-Domain Comparator for Input-Referred Noise Reduction.
13. A study on methods for improving the straightness of the intelligent walker to move on slope.
14. A 5.4 Gb/s clock and data recovery circuit using the seamless loop transition scheme without phase noise degradation.
15. A high resolution metastability-independent two-step gated ring oscillator TDC with enhanced noise shaping.
16. A Spread Spectrum Clock Generator with Spread Ratio Error Reduction Scheme for DisplayPort Main Link.
17. Authenticated On-Demand Ad Hoc Routing Protocol without Pre-shared Key Distribution.
18. Modeling of Policy-Based Network with SVDB.
19. A LOG-Induced SSN-Tolerant Transceiver for On-Chip Interconnects in COG-Packaged Source Driver IC for TFT-LCD.
20. A Unified Graphics and Vision Processor With a 0.89 µW/fps Pose Estimation Engine for Augmented Reality.
21. A 5.4/2.7/1.62-Gb/s Receiver for DisplayPort Version 1.2 With Multi-Rate Operation Scheme.
22. A 5.4-Gb/s Clock and Data Recovery Circuit Using Seamless Loop Transition Scheme With Minimal Phase Noise Degradation.
23. An Adaptive Equalizer With the Capacitance Multiplication for DisplayPort Main Link in 0.18-µm CMOS.
24. A Spread Spectrum Clock Generator for DisplayPort Main Link.
25. Object-oriented software for diagnosis of manufacturing systems.
26. A 6.4Gb/s/pin at sub-1V supply voltage TX-interleaving technique for mobile DRAM interface.
27. A graphics and vision unified processor with 0.89µW/fps pose estimation engine for augmented reality.
28. A diagnosis scheme for a large-scale system.
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