35 results on '"Yasumasa, Tsukamoto"'
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2. Study of Local BTI Variation and its Impact on Logic Circuit and SRAM in 7 nm Fin-FET Process.
3. NBTI/PBTI separated BTI monitor with 4.2x sensitivity by standard cell based unbalanced ring oscillator.
4. A 7nm Fin-FET 4.04-Mb/mm2 TCAM with Improved Electromigration Reliability Using Far-Side Driving Scheme and Self-Adjust Reference Match-Line Amplifier.
5. A 28-nm 1R1W Two-Port 8T SRAM Macro With Screening Circuitry Against Read Disturbance and Wordline Coupling Noise Failures.
6. A 5.92-Mb/mm2 28-nm pseudo 2-read/write dual-port SRAM using double pumping circuitry.
7. A Fully Standard-Cell Based On-Chip BTI and HCI Monitor with 6.2x BTI sensitivity and 3.6x HCI sensitivity at 7 nm Fin-FET Process.
8. A 28nm high density 1R/1W 8T-SRAM macro with screening circuitry against read disturb failure.
9. A cost-effective 45nm 6T-SRAM reducing 50mV Vmin and 53% standby leakage with multi-Vt asymmetric halo MOS and write assist circuitry.
10. A Test Screening Method for 28 nm HK/MG Single-Port and Dual-Port SRAMs Considering with Dynamic Stability and Read/Write Disturb Issues.
11. Optimization of importance sampling Monte Carlo using consecutive mean-shift method and its application to SRAM dynamic stability analysis.
12. Quasi-Planar Tri-gate (QPT) bulk CMOS technology for single-port SRAM application.
13. A stable chip-ID generating physical uncloneable function using random address errors in SRAM.
14. A dynamic body-biased SRAM with asymmetric halo implant MOSFETs.
15. Dynamic stability in minimum operating voltage Vmin for single-port and dual-port SRAMs.
16. Study of impact of BTI's local layout effect including recovery effect on various standard-cells in 10nm FinFET.
17. 28 nm 50% Power-Reducing Contacted Mask Read Only Memory Macro With 0.72-ns Read Access Time Using 2T Pair Bitcell and Dynamic Column Source Bias Control Technique.
18. A 65nm Embedded SRAM with Wafer-Level Burn-In Mode, Leak-Bit Redundancy and E-Trim Fuse for Known Good Die.
19. A 45nm Low-Standby-Power Embedded SRAM with Improved Immunity Against Process and Temperature Variations.
20. Worst-case analysis to obtain stable read/write DC margin of high density 6T-SRAM-array with local Vth variability.
21. A 32×24-bit multiplier-accumulator with advanced rectangular styled Wallace-tree structure.
22. A 0.41 µA Standby Leakage 32 kb Embedded SRAM with Low-Voltage Resume-Standby Utilizing All Digital Current Comparator in 28 nm HKMG CMOS.
23. A 28nm 360ps-access-time two-port SRAM with a time-sharing scheme to circumvent read disturbs.
24. A 28 nm Dual-Port SRAM Macro With Screening Circuitry Against Write-Read Disturb Failure Issues.
25. Synchronous Ultra-High-Density 2RW Dual-Port 8T-SRAM With Circumvention of Simultaneous Common-Row-Access.
26. A 65 nm Embedded SRAM With Wafer Level Burn-In Mode, Leak-Bit Redundancy and Cu E-Trim Fuse for Known Good Die.
27. A 45-nm Bulk CMOS Embedded SRAM With Improved Immunity Against Process and Temperature Variations.
28. A 45 nm 2-port 8T-SRAM Using Hierarchical Replica Bitline Technique With Immunity From Simultaneous R/W Access Issues.
29. A 65-nm SoC Embedded 6T-SRAM Designed for Manufacturability With Read and Write Operation Stabilizing Circuits.
30. A 90-nm low-power 32-kB embedded SRAM with gate leakage suppression circuit for mobile applications.
31. A 512-kb 1-GHz 28-nm partially write-assisted dual-port SRAM with self-adjustable negative bias bitline.
32. 13.3 20nm High-density single-port and dual-port SRAMs with wordline-voltage-adjustment system for read/write assists.
33. 1.8 Mbit/mm2 ternary-CAM macro with 484 ps search access time in 16 nm Fin-FET bulk CMOS technology.
34. 3-D numerical modeling of thermal flow for insulating thin film using surface diffusion.
35. A 0.5V 100MHz PD-SOI SRAM with enhanced read stability and write margin by asymmetric MOSFET and forward body bias.
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