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Doped-multilayer-graphene (DMLG) interconnects employing the subtractive-etching (SE) process have opened a new pathway for designing interconnects at advanced technology nodes, where conventional metal wires suffer from significant resistance increase, self-heating (SH), electromigration (EM), and various integration challenges. Even though single-level scaled graphene wires have been shown to possess better performance and reliability with respect to dual-damascene (DD) and SE-enabled metal wires, a multi-level graphene interconnect technology (with vias) has remained elusive, which is of paramount importance for its integration in future technology nodes. This work, for the first time, addresses that need by engineering a CMOS-compatible solid-phase growth technique to yield large-area multilayer graphene (MLG) on dielectric (SiO2) and metal (Cu) substrates and subsequently demonstrating multi-level MLG interconnects with metal vias. Using rigorous theoretical and experimental analyses, we demonstrate that multi-level MLG interconnects with metal vias undergo < 2% change in the via resistance under accelerated stress conditions, demonstrating its superior reliability against SH and EM, making them ideal candidates for sub-10 nm nodes.

Domain walls in multiferroics can exhibit intriguing behaviors that are significantly different from the bulk of the material. We investigate strong magnetoresistance in domain walls of the model multiferroic BiFeO3 by probing ordered arrays of 109° domain walls with temperature- and magnetic-field-dependent transport. We observe temperature-dependent variations in the transport mechanism and magnetoresistances as large as 60%. These results suggest that by locally breaking the symmetry of a material, such as at domain walls and structural interfaces, one can induce emergent behavior with properties that deviate significantly from the bulk.