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This paper presents a survey and classification of architectures for integrated circuit implementation of digital pulse-width modulators (DPWM) targeting digital control of high-frequency switching DC-DC power converters. Previously presented designs are identified as particular cases of the proposed classification. In order to optimize circuit resources in terms of occupied area and power consumption, a general architecture based on tapped delay lines is proposed, which includes segmentation of the input digital code to drive binary weighted delay cells and thermometer-decoded unary delay cells. Integrated circuit design of a particular example of the segmented DPWM is described. The segmented DPWM prototype chip operates at 1 MHz switching frequency and has low power consumption and very small silicon area (0.07 mm/sup 2/ in a standard 0.5 micron CMOS process). Experimental results validate the functionality of the proposed segmented DPWM.

In digitally controlled DC-DC converters with a single voltage feedback loop, the two quantizers, namely the A/D converter and the digital pulse-width modulator (DPWM), can cause undesirable limit-cycle oscillations. In this paper, static and dynamic models that include the quantization effects are derived and used to explain the origins of limit-cycle oscillations. In the static model, existence of DC solution, which is a necessary no-limit-cycle condition, is examined using a graphical method. A concept of amplitude and offset dependent gain is introduced to extend the describing function method and derive the dynamic system model. From the static and dynamic models, no-limit-cycle conditions associated with A/D, DPWM and compensator design criteria are derived. The conclusions are illustrated by simulation and experimental examples.

This paper presents a low-ripple topology for switching power converters that approximates the ideal ripple-free averaged dynamics by means of reactive passive tuned filters. The low-ripple characteristics can be taken advantage of to either improve the suitability of the switching power converter to supply ripple-sensitive loads, or to reduce the value of the converter main filtering capacitor. The work explores this second property in the context of pursuing further miniaturization and particularly on-chip circuit integration of a switching power converter. Experimental results for a low frequency prototype demonstrate the functionality of the proposed low-ripple topology, showing in particular a reduction of a factor of seven for the main capacitor in the converter.