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We present two case studies of different architectures for H.264 video decoder. The objective of this case study is to show the design methodology that can maximize the flexibility of video decoder. First, H.264 is designed based on configurable processor. The configurable processor was used to complement the existing functional units with instruction extensions for the H.264 hardware kernel. Secondly, we profile the H.264 application to capture the amount of data traffic among modules. We will use this information to guide the placement of H.264 hardware modules in the dataflow architecture. A simulated annealing based placement algorithm produces the final placement aiming to optimize the communication costs between the modules in a dataflow architecture. With both our design methodologies, emerging embedded applications requiring several GOPS to meet real-time constraints can be drafted within a reasonable amount of design time with maximum design flexibility

There are many applications within digital signal processing (DSP) that require the user to know how various numerical errors (uncertainty) affect the result. This uncertainty is represented by replacing non-interval values with intervals. Since most DSPs operate in real time environments, fast processors are needed to implement interval arithmetic. The goal is to develop a platform in which interval arithmetic operations are performed at the same computational speed as present day signal processors. We have proposed a design for an interval based arithmetic logic unit (I-ALU) whose computational time for implementing interval arithmetic operations is equivalent to many digital signal processors. Many DSP and control applications require a small subset of arithmetic operations that must be computed efficiently. This design has two independent modules operating in parallel to calculate the lower bound and upper bound of the output interval. The functional unit of the ALU performs the basic fixed-point interval arithmetic operations of addition, subtraction, multiplication and the interval set operations of union and intersection. In addition, the ALU is optimized to perform dot products through the multiply-accumulate instruction. Division traditionally is not implemented on digital signal processors unless computed with a shift operation. In this design, division by shifting is implemented. The ALU is designed to have maximum throughput while minimizing area.