1. A Cost-Effective Low Power Platform for the 45-nm Technology Node
- Author
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N. Cave, Vincent Huard, C. Monget, C. Le Cam, S. Zoll, S. Parihar, S. Bordez, F. Guyader, D. Delille, N. Auriac, Michel Haond, R. Pantel, B. Icard, M. Zaleski, S. Harrison, A. Margain, C. Blanc, Scott Warrick, D. Barge, J. Belledent, D. Villanueva, Francois Leverd, G. Ribes, E. Baylac, Alexis Farcy, C. Laviron, Kathy Barla, E. Perrin, K. Rochereau, M. Bidaud, S. Manakli, Pascal Gouraud, Laurent Pain, O. Callen, Blandine Minghetti, Emmanuel Josse, Paulo Ferreira, and R. Ranica
- Subjects
Materials science ,business.industry ,Transistor ,Electrical engineering ,Hardware_PERFORMANCEANDRELIABILITY ,AC power ,law.invention ,Reliability (semiconductor) ,Strain engineering ,law ,Gate oxide ,Hardware_INTEGRATEDCIRCUITS ,Power semiconductor device ,Electronics ,Static random-access memory ,business - Abstract
This paper presents a cost-effective 45-nm technology platform, primarily designed to serve the wireless multimedia and consumer electronics needs. This platform features low power transistors operating at a nominal voltage of 1.1V, an ultra low k dielectric (k~2.5) with up to 9 Cu metal layers and 0.25/0.3/0.37mum2 SRAM cells. This platform also features an optional third gate oxide for either higher speed or active power mitigation. This technology has been developed on the (100)-oriented substrate with a key focus on process simplicity. Transistor improvement relies on mask-free strain engineering techniques along with co-implanted halos and laser anneal. The impact of laser anneal on transistor reliability and mixed-signal capabilities are also examined. Drive current as high as 660/320 muA/mum at 1nA/mum and 1.1V are reported
- Published
- 2006
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