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Linearity is an important measurement for the performance of a CMOS low noise amplifier (LNA). The high computational cost required in the linearity simulation, however, constitutes a major bottleneck in the design verification stage. In this paper, we develop a novel and systematic geometric programming (GP)-based approach for the optimized design of a highly linear CMOS LNA, subject to the minimization of the noise factor. Experiments confirm the remarkable efficacy and accuracy of the proposed design flow against traditional simulators.

We study model order reduction (MOR) of continuous-time linear time-varying (LTV) systems. Examples include circuit or interconnect models found in VLSI marco-modeling. Specifically, a time-varying version of positive-real balanced truncation (PRBT), called LTV-PRBT, is proposed, which preserves the passivity of LTV systems for stable global simulation. Implementation details are discussed together with a brief outline of a discrete-time counterpart of LTV-PRBT. Dynamically changing state dimension is allowed for accurate modeling at the lowest possible order. Numerical examples then verify the effectiveness of the proposed approach over existing LTV MOR methods.