1. Novel Diffusion Topography Engineering (DTE) for High Performance CMOS Applications
- Author
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W.Y. Teo, M.T. Yang, W.C. Lee, C.W. Kuo, C.Y. Fu, C.H. Ge, Hung-Wei Chen, H.N. Lin, Ding-Yuan Chen, C.C. Chen, and Chih-Hsin Ko
- Subjects
Stress (mechanics) ,Superposition principle ,Reliability (semiconductor) ,Materials science ,CMOS ,Nanoelectronics ,Electronic engineering ,Diffusion (business) ,NMOS logic ,PMOS logic - Abstract
The concept of diffusion topography engineering (DTE) is proposed and exercised on state-of-the-art 65 nm technology for the first time. Diffusion region extended over STI and therefore resulting in T-shape diffusion profile is created purposely to suppress STI stress and oxide divot. This novel technique delivers up to 33% PMOS and 22% NMOS enhancement, respectively, and results in -10% R.O. speed improvement. When combined with high-stress contact-etch-stop-layer (CESL) , a significant 27% CMOS enhancement is achieved through preferable strain superposition. Both device integrity and reliability are carefully evaluated and neither of them is adversely impacted by DTE.
- Published
- 2007