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To simplify the system integration, thermal design and wiring of the SNAP satellite focal plane a custom IC has been developed that can digitize the four output channels of a CCD. This CCD readout IC is designed to operate at room temperature for test purposes and at 140 K, the operating temperature of the focal plane. The chip consists of four-channels of pre-amplifier, double correlated sampler and 14-bit pipeline AD converter. The chip incorporates an innovative circuitry that selects one of three gain levels on a per-pixel basis to achieve greater than 16-bit dynamic range. It has an on-chip voltage reference and programmable configuration registers. We have tested the performance both at room temperature and at 140 K, as well as the radiation tolerance. The ASIC, implemented in a standard 0.25 mum CMOS technology, has a measured readout noise of 6.2 muV rms at 100 kHz readout speed, a measured non-linearity of plusmn5 LSB and a power consumption of 121 mW.

An ASIC designed to provide the clock signals to the focal plane CCDs for the SNAP satellite project is presented. A prototype has been implemented in a CMOS 0.8 mum SOI high voltage process in order to accommodate a 20 V output swing. The circuit consists of a main charge pump multiplying the 4 V power supply voltage +/-16 V followed by a controlled current source setting the clock voltage plateaus. A bridge of switches provides the clock voltage transitions at the output. This circuit is designed to operate at room temperature for test purpose and at 140 K, which will be the operating temperature. Novel design techniques used in this chip will be presented in detail along with measurement results obtained on the prototypes.

We have developed scientific charge-coupled devices (CCDs) that are fabricated on high-resistivity, n-type silicon substrates, and have demonstrated fully depleted operation for substrate thicknesses of 200-675 mum with formats as large as 2048 times 4096 (15 mum pixels) and 3512 times 3512 (10.5 mum pixels). The main application area for these devices is space and ground-based astronomy, and the CCDs are operated at cryogenic temperatures with slow-scan readout for good performance in terms of dark current and noise. In this work we describe the technology development efforts needed to realize a 4k times 4k (15 mum pixel) CCD with a die area of (64 mm)2. In particular, we describe improved gettering techniques for low dark current and high charge transfer efficiency that have been developed in order to improve fabrication yields for these very large format CCDs.