1. Manufacturability and Speed Performance Demonstration of Porous ULK (k=2.5) for a 45nm CMOS Platform
- Author
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G. Huang, R. Delsol, M. Rasco, N. Cave, A. Perera, L. Marinier, Michel Haond, A. Guvenilir, A. Lagha, M. Mellier, C. Monget, C. Cregut, G. Imbert, E. Richard, M. Guillermet, Paulo Ferreira, Sébastien Petitdidier, S. Downey, Robert Fox, M. Zaleski, W. Besling, E. Oilier, P. Brun, and Lucile Broussous
- Subjects
Materials science ,CMOS ,Resist ,Optical proximity correction ,business.industry ,Etching (microfabrication) ,Electronic engineering ,Optoelectronics ,Dielectric ,business ,Lithography ,Numerical aperture ,Design for manufacturability - Abstract
A full ULK (ultra low-k) integration using TFHM (trench first hard mask) architecture (Hinsiger et al., 2004) is demonstrated in a high density CMOS 45 nm device. 13 nm-pitch metal features have been resolved using a 193 nm immersion hyper-NA (numerical aperture) scanner and an optimized OPC (optical proximity correction) model. RC performance and yield results are presented for a fully-integrated 45 nm ULK backend. An overall speed performance enhancement of >10% has been confirmed within a microprocessor application at the 65 nm technology node when replacing Low-k dielectric (k=2.9) with ULK (k=2.5) material.
- Published
- 2007
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