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Flash memory is a kind of common storage device. Its characteristics of flexibility, low power, and so on offer excellent qualifications for embedded system and mobile system. But flash memory must be written after erasure operation, and the most important thing is that the erasure operation times are very limitable. For assurance of long time availability, data must be distributed over all memory space reasonably and politic, which brings forward challenge for storage system designer. This paper analyses the data structure and physical characteristics of typical flash memory. And a static trigger wear-leveling strategy based on classifying data with trigger condition is brought forward, called STWL. STWL forces these static data to move over all memory space according to the trigger condition so as to avoid some certain data blocks being damaged in advance. An experiment is carried out to simulate this strategy using VHDL. We construct a 4M bytes RAM as flash memory simulation model, a static wear-leveling unit to implement STWL and an excitation generation unit to yield memory store/load operations, As a result, the wear-leveling rate improves. 33% of space recycle times can be reduced and the biggest gap of number of erasing times of data block decreases from 883% to 38%.