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This paper presents a practical method to estimate IC product performance and parametric yield solely from a well-chosen set of existing electrical measurements intended for technology monitoring at an early stage of manufacturing. We demonstrate that the components of mmWave PLL and product-like logic performance in a 65 nm SOI CMOS technology are predicted within a 5% RMS error relative to mean.

A wideband millimeter-wave (mmWave) CML static divider fabricated in 65 nm SOI CMOS technology is presented. The mmWave system realization trend and engagement in sub-100 nm CMOS technologies are summarized. CML static dividerpsilas circuit analysis, sensitivity curve, and simulations are explored. The input-locking hysteresis and divider DC bias tuning are employed to extend the divider operation range. The divider performance measurements are presented with hysteresis-assisted gain and figure-of-merits. A scalable statistical estimation is proposed, and it is validated with a full 300 mm wafer measurements. The divider exhibits wideband mmWave performance to overcome the process variability in sub-100 nm CMOS processes.