Search

This paper addresses quantization noise shaping using sigma-delta (SigmaDelta) modulators in switched-mode power converters with digital pulse-width modulation (DPWM). It is shown that the SigmaDelta modulator design must take into account the effects of idle tones and DPWM nonlinearities, as well as the converter switching frequency and output filter constraints. Best results are obtained using 2nd order or higher order SigmaDelta modulators in combination with center (dual-edge) DPWM. As an example, in an experimental synchronous buck power converter operating at 781 kHz and having a 4-bit center DPWM, a 44 dB reduction of the maximum noise spectral component over the 1st order modulator is obtained using a modified 3rd-order SigmaDelta modulator. Various design trade-offs are examined and limits of achievable DPWM resolution improvements are found as a guide to practical realizations of high-frequency digital controllers for DC-DC converters.

This paper addresses the fully monolithic integration of a 3-level 2-phase buck converter for DC-DC step-down conversion in standard CMOS. First it is shown a design-oriented analysis of the converter considering DCM mode (due to PFM operation for low output currents) and with low values of the floating capacitor (to improve integrability). At transistor-level, a self-driving scheme is proposed which allows supplying the tapered buffer drivers from the floating capacitor, thereby reducing the voltage across the power MOSFETs gate dielectric and improving efficiency. The presented converter exhibits enhanced degrees of freedom in the design space defined by the switching frequency, inductor and capacitors values, which have an impact on the achievable efficiency, occupied silicon area and output ripple. An optimized design exploration is carried out for V bat = 3.6 V, Vo = 1 V, Io = 100 mA, DeltaVo = 50 mV, which yields a converter with the following main characteristics: L = 20.9 nH, Co = 18.6 nF, Cx = 3.8 nF and/s = 51.79 MHz (for Io = 100 mA), a power efficiency of 68.51 % and a occupied area of 3.77 mm2, which results in a clear improvement when the same structured design method is applied to classical buck converter. However, finally a lower switching frequency design is selected to be implemented to allow control loops operation (fs = 37.28 MHz). After providing details of the layout design, full-transistor level simulation results validate the improved performance and the efficiency model. Experimental results from an implemented IC validate the time-domain functionality of the on-chip converter.