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The proposed on-die termination (ODT) calibration method is implemented by using a 0.18um CMOS technology. The proposed ODT can detect the impedance variations of each ODT/OCD independently with the help of the proposed local PVT variation sensor and can decrease the impedance mismatch error lower than 1% by calibration of global on-chip variation with small area overhead. The measured eye diagram area at 2Gbps is widened by 26% when the ODT is on. The random data rate used for testing the eye diagram is 2Gbps. The global impedance mismatch error is within 1% under the supply voltage variation from 1.7V to 1.9V. The ODT and its calibration circuit occupy 0.003mm2 and 0.015mm2, respectively. The power consumption of the calibration circuit is 10mW at 2Gbps.

An ADPLL with a piecewise linear calibrated hierarchical TDC is proposed to achieve a wide range of operation and a CPPLL is cascaded to filter out 1/f noise. A phase selectable divider is also proposed to divide the clock frequency while keeping the relative phase difference of output same as that of input. The cascaded hybrid PLL fabricated in 65nm CMOS process burns 17mW and occupies 0.4mm2. The measured jitters are 1.1ns pp and 223.6ps rms , respectively with a multiplication factor of 1,024.

This paper presents the design of a 64-PE folded-torus intra-chip communication fabric used to provide guaranteed throughput in terms of dead- and live-lock free and in-order data delivery, which is suitable for NoC-based real-time processing applications. A test chip using the proposed intra-chip communication fabric designed to integrate 64 RISC-based processing elements is fabricated in 1P6M 0.13µm CMOS technology with 23mm2 die area. At room temperature, the measured peak power (all PE-tiles activated) of the test chip is 200mW @ 128MHz at 1.2V cc . The intra-chip network consuming 9. 4% the chip area and 18% of the total chip power can provide a maximum bisection bandwidth of 44.6Gb/s with an approximate energy per transported bit of 0.14 pJ/bit/hop.

The proposed temperature sensor is based on CMOS ring oscillators and a frequency-to-digital converter capable of simple and efficient temperature conversion to digital value. The proposed temperature sensor consumes 400uW at a conversion rate of 366kS/s and performs the fastest temperature-to-digital conversion among those introduced in previous work. The whole block occupies 0.0066 mm2 (0.0013 mm2 for temperature sensor). Four multiphase clocks were utilized to enhance the resolution of the sensor 8 times better. After one point calibration, the chip-tochip measurement spread was +2.748°C ∼ −2.899°C over the temperature range of −40°C to 110°C.