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One-transistor (1T) memory cells with long data retention time is achieved with the modulation of drain current by channel traps. For simple demonstration, poly-Si TFTs are used, and grain boundary traps induced by excimer laser annealing are used as channel traps. The channel length in this work is 6 μm and the extrapolated data retention time can be as long as ~107 s at half of the current window. With the assumption that total number of traps is proportional to device volume and leakage current is proportional to the peripheral areas, retention time is scaled with gate length. For 30 nm devices, retention time is estimated to be ≥ 5×104 s. Compared with the conventional Zero-capacitor random access memory (Z-RAM), the channel trap memory provides better retention characteristics. For practical applications, the new channel trap cell has the same gate structure as logic devices, and can be potentially embedded in SoC platform. Due to the defect tolerance of cell channel and the low-temperature process, the 3D (multi-layer) memory structure by stacking the cells vertically can be potentially implemented more easily than flashtype devices [1]. In principle, the channel traps cells can also be implemented in bulk Si and the localized channel traps can be formed in the scaled devices using implantation techniques. This paper proposes a design of 1T memory cells that utilizes the modulation of drain current by channel traps and offers these advantages: 1. capacitorless structure, 2. long data retention time, 3. excellent endurance characteristics, 4. low power consumption, 5. 3D integration compatibility.