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Today high speed signal transmission system for on chip global interconnect requires elaborate design of the transceiver. The design goal of transceiver is to ensure the transmission obtains an improvement in latency and power, which are the two most important factors in high speed transmission. In this paper, we present an efficient structured transceiver which implements low swing technology based on the differential structure with the accurate modeling of the on chip global interconnect. And we give the principals of the structure and compare the optimized simulation results with the traditional inverter insertion method used to decrease the delay of the global interconnect. Our transceiver design is based on the 90nm CMOS technology and TSMC 90nm interconnect structure on Metal 5. The global interconnect length we focus on is the general length 10mm. Compared to repeater insertion, this system has a latency advantage of 17% and remarkable advantage in power up to 33.9%.

Standard cache memories exploit 1-D spatial locality which will suffer great performance penalty when applied to multimedia that manifests 2-D data dependence. History-based prefetching policies have been proposed to tailor cache memories to multimedia applications. Such schemes, however, are driven by the instruction address, which means it needs a significantly large prediction table for instruction caching. In this paper we propose a novel data address directed scheme to pure hardware prefetching. The prefetching scheme is modeled and evaluated at transaction level (TLM) based on Carbon SoC Designer. The experimental results show that data address directed prefetching-on-miss policy can significantly reduce cache miss rate by up to 23.8% with only a small prediction table.

A Simulated Annealing Genetic Algorithm (SAGA) with greedy mapping mechanism is developed to solve task partitioning problems in coarse grain reconfigurable systems. A fitness function combined multiple objectives (communication cost, number of partitions and number of bypass nodes) is constructed to optimize the execution time. Experimental results show that SAGA produces better solutions than traditional level-based or clustering-based partitioning algorithm. The operation time saved is up to 5% compared with level-based algorithm, and critical parameters such as communication cost and number of partitions are reduced by 10% in average.

Recent embedded systems have switched to parallel microprocessors. Linear array processors and 2-D array processors are two classifications for the processing element (PE) interconnection. The former have better expansibility and greater throughput while the later have better communication efficiency. In order to improve the communicat ion efficiency without losing expansibility, this paper introduces RLAP, a reconfigurable linear array processor architecture, targeted at data parallel and computation intensive applications in the video domain. Compared with the conventional linear array processors, the performance of RLAP improves by 8.7 times, 104% and 10.8% for the applications of 8×8 matrix transpose, 8×8 DCT and 16×16 SAD.