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Ever-growing demand for higher communication bandwidth in high performance compute systems is driving the need for energy-efficient multi-Gb/s I/O serial links. Improved power efficiency was demonstrated using adaptive supply regulation [1, 2]. However, power losses in the DC-DC converter needed to generate the optimal supply voltage and the difficulty in operating analog circuits at low voltages limit the power savings. Instead of scaling the supply with the data rate, we seek to operate with two fixed voltages and eliminate the need for a high-efficiency DC-DC converter. To this end, this paper presents a serial link using a highly efficient current recycling-based implicit DC-DC conversion to generate 0.6V from a 1.2V supply. Highly digital clocking circuits capable of operating at 0.6V maximize power savings. A 0.5-to-4Gb/s serial-link transceiver is designed in a 1.2V LP 90nm CMOS process to operate with a short channel and ple-siochronous timing. The transceiver dissipates 1.9mW/Gb/s at 3.2Gb/s.

Digital phase-locked loops (DPLLs) have recently emerged as a viable alternative to classical charge-pump analog PLLs [1–4]. By obviating the need for a large loop filter capacitor and a high-performance charge pump, DPLLs offer area savings and easier scalability to newer processes. The ability to reconfigure the digital loop filter dynamically offers flexibility in setting the loop response and helps to optimize the locking behavior of the DPLL [1]. However, conflicting bandwidth requirements to simultaneously suppress TDC quantization error and oscillator phase noise mandate either a high-resolution TDC or a low-noise oscillator to minimize jitter [2]. Further, much like in an analog PLL, the ring oscillator is susceptible to supply noise, which especially limits the jitter performance of a DPLL integrated into a large digital system. A low-dropout regulator is commonly used to shield the DCO from supply noise at the expense of additional area, power, and voltage headroom [3]. Alternatively, an open-loop supply-noise cancellation scheme can operate at a lower supply voltage, but its accuracy is highly sensitive to process variations [5]. Analog foreground calibration compensates for process variation but is susceptible to voltage, temperature, and frequency variations [6]. In this paper, we present a deterministic test-signal-based background calibration scheme that leverages the highly digital nature of the DPLL to adaptively cancel the supply noise in the DCO. The prototype DPLL achieves nearly perfect supply-noise cancellation over an output frequency range of 0.4 to 3GHz while consuming 2.65mW at 1.5GHz.

Clock and data recovery (CDR) circuits with wide frequency acquisition range offer flexibility in optical communication networks, help reduce link power through activity-based rate adaptation, and minimize cost with a single-chip multi-standard solution. Extracting the bit rate from the incoming random data stream is the main challenge in implementing reference-less CDRs. A conventional rotational frequency detector has a limited acquisition range of about ±50% of the VCO frequency, consumes large power, and is susceptible to harmonic locking. Extending its range requires additional high-speed circuitry and a complex state machine [1]. The DLL-based architecture in [2] requires passing high-speed data through a long string of power-hungry buffers, imposes stringent matching requirements, and works only with ring oscillators. Other approaches require detailed statistical [3] or timing analysis [4]. Further, all the above techniques are only suitable for full-rate CDRs. In this paper, we present a reference-less half-rate CDR that uses a sub-harmonic extraction method to achieve unlimited frequency acquisition range. This technique is capable of locking the CDR to within 40ppm of any sub-rate of the data (making it applicable for any sub-rate CDR architecture), while being immune to undesirable harmonic locking. This CDR also integrates a calibration loop to improve robustness to input duty cycle error.