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Depositing ultra-thin metallic films with an accurate control of the film properties (like film thickness, surface roughness and electrical properties) both in the initial and in the progressed film growth regime is a critical challenge. Monitoring atomic layer deposition processes by spectroscopic ellipsometry allows film thickness control in the sub-nanometer range. In addition, ellipsometry serves as a powerful technique for process analysis as it covers many relevant issues, like the evaluation of substrate temperatures as well as the quantification of film properties during the entire ALD process (i. e. in all relevant growth regimes).

In the back end of line (BEOL) processing of advanced microprocessors several levels (ten or more) of wiring and associated via (interconnects) are required. Through these wiring-via levels signal and power can be carried throughout the chip and to the chip carrier. The semiconductor industry uses the dual damascene approach to fabricate a wiring- and a via-level simultaneously. However, the dual damascene processing requires more than twenty process steps for one wiring-via level. For an advanced microprocessor with more than ten wiring-via levels the step count for interconnects exceeds that for front end processing. Currently, the dual damascene processing is becoming the most time-consuming step in the processing sequence and affects the throughput of the semiconductor industry essentially. In this work we present a novel approach to fabricate a multi-tier structure for dual damascene processing based on UV nanoimprint lithography (UV-NIL). By using a soft polymer (PDMS) template with multi-tier patterns, a dual damascene structure for one wiring level and one via level can be directly imprinted in a functional dielectric material simultaneously. This UV-NIL based dual damascene processing reduces the total process steps drastically. The possibility of UV-NIL for dual damascene processing and imprintable dielectric materials as interlayer dielectric (ILD) will be discussed.

The use of Through Silicon Via (TSV) extends to different areas of electronics. Besides its utilization for logic and memory chips, a growing attention has been spent to sensor applications in the last years. Each application has its specific requirements which affect the whole processing scheme. Typically TSV's are generated by filling blind holes with copper and thinning the wafer afterwards, or by coating through holes with copper. Here we present an alternative concept which can be applied for biochemical sensors, so that a blind hole is created stopping on a SiO 2 membrane. By this the need for a post wafer thinning is avoided.