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An extensible postprocessor architecture of a new algorithm is presented in this paper to correct the timing skew in 7-channel time-interleaved ADCs. The Least Mean Squares (LMS) algorithm is utilized to identify the timing skew, which is used to compensate digital output according to its high order Taylor expansion. FPGA synthesis results show that, with ±0.02Ts timing skew, and normalized input frequency fin/fs=0.47, signal-to-noise-and-distortion ratio and spurious-free dynamic range of the TIADC after calibration reach 85.7dB and 96.8dB, improved by 50dB and 54dB respectively, compared to the uncalibrated digital outputs. The circuit based on the proposed architecture is simple and easily extensive to TIADC with different number of split-ADCs.

An analysis of performance degradation due to limited precision of reference voltage for pipelined ADC (Analog to Digital Converter) is presented in this paper. For the MDAC (multiplying D/A converter) and subADC in pipelined ADC have very different requirements for the precision of reference voltage, an improved differential reference voltage source and its buffer circuit is proposed. The reference voltage for MDAC and subADC are provided and designed the output buffer separately, so that to reduce the crosstalk between MDAC and subADC. Also, the driving ability of the proposed circuit is controllable with the help of programmable bias circuit which regulates the circuit's entire power consumption. Spectre post-layout simulation results show that the reference source has the minimum power of 15mW, and the entire set-up time is 5.842ns; has the maximum power of 58mW, and the entire set-up time is 1.036ns. The reference source can meet the requirement of 14-bit 80MSPS to 450MSPS pipelined ADC.