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With the growing scale of integration, design of circuits with power consumption has become the primary motivation for the development in sub-threshold region. The circuits operating in sub threshold results in ultra-low power due to the use of leakage current which is in the order of nano amperes as the operating current. In many high speed applications, compressors are used to perform the partial product addition needed during multiplication. In this paper two architecture for 4∶2 and 5∶2 compressors in the sub threshold region is proposed. The paper aims at comparing the power consumption, delay and the power-delay product (PDP) of the two architectures in the sub threshold region. All the simulations have been performed using 0.18um CMOS technology parameters. [ABSTRACT FROM PUBLISHER]