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The implementation of a “superjunction” collector design in a silicon-germanium heterojunction bipolar transistor is explored for enhancing breakdown performance. The superjunction collector is formed through the placement of a series of alternating pn-junction layers in the collector-base space charge region to modify the carrier energy profile and reduce avalanche generation. An overview of the physics underlying superjunction collector operation is presented with TCAD simulations, and practical superjunction design techniques are discussed. The first measured data on a superjunction collector is also presented and shows a 57% improvement in breakdown performance.

High-current pulsed stress measurements are performed on SiGe HBTs to characterize the damage behavior and create a comprehensive physics-based TCAD damage model for Auger-induced hot-carrier damage. The Auger hot-carrier generation is decoupled from classical mixed-mode damage and annealing on the output plane by using pulsed stress conditions to modulate the self-heating within the device under stress. The physics of high-current degradation is analyzed, and a temperature dependent degradation model is presented. This model is the first of its kind in both the CMOS and bipolar communities and solves a significant portion of the puzzle for predictive modeling of SiGe HBT safe-operating-area (SOA) and reliability.