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A 10 GHz 4-phase ring-VCO based injection-locked clock multiplier (RILCM) for 40 Gb/s SerDes application is presented in this paper. The RILCM adopts two loops which share common part circuit to realize the injection lock. The first loop which is the frequency lock loop (FLL), drags the VCO's free-running frequency to the injection lock-in range. Another loop which is the injection timing control loop (ITCL), controls the injection timing of the pulse to reduce the race condition and improve the phase noise. The RILCM is designed in a 65nm CMOS technology and supplied with 1.1V. The simulation results show that the proposed RILCM can provide 4-phase 10 GHz clocks with 3.61ps total jitter, at this time the total consumption is 17 mW.

This paper describes the design of a serial-link transceiver that supports various communication standards from 1.25 to 12.5Gb/s, implemented in 40nm CMOS technology. Both DC and AC coupling mode can be provided by the receiver, in which a wide range PI-based CDR is also proposed. The transceiver utilizes a 3-tap FFE, a 2-stage CTLE and an adaptive 2-tap DFE to achieve the compensation for a Nyquist channel loss of 32.4dB, and consumes 66mW from a 1.1V supply when operating at 12.5Gb/s.

This paper presents a 28Gbps voltage controlled oscillator (VCO) based clock and data recovery (CDR) with a separate proportional path technology. It employs a quarter rate ternary Bang-Bang phase detector to extract the phase error between the local clock and input data. The circuit designed in a 65nm CMOS process achieves ±1000 ppm lock-in rang, ±6000 ppm tracking range. The simulation results show that the total jitter of the recovered clock is 4.7ps when the CDR locked at 28 Gb/s. In addition, this CDR can track a 500 KHz sinusoidal phase jitter with 2UI amplitude.

An 80 Gb/s 4-level pulse amplitude modulation (PAM4) wireline receiver is presented in this paper. This receiver adopts quarter rate architecture to improve data rate and reduce power consumption. In order to reduce the complexity of the clock and data recovery (CDR) design, a voltage control oscillator (VCO) based CDR without reference clock is used. Furthermore, four BBPDs are used to sample the edge and data information generated by the middle slicer for extraction the phase error between the data and clock. The receiver is designed in 65nm CMOS technology and supplied with 1.2V. The simulation results show that the proposed PAM4 receiver can work at 80 Gb/s with 235mW consumption.

This paper presents a low phase noise ring voltage controlled oscillator (ring VCO) based on two differential delay cells with cross-coupled MOSFET pair which provide proper initial condition and sustain oscillating. The phase noise of VCO has been improved by using MOSFETs working in linear region as voltage controlled devices instead of working in saturation region (current source). Besides, the cross-coupled pMOS pairs was adopted instead inverters to save power. The VCO was designed in SMIC 40nm CMOS technology, covering a wide tuning range of 8-11GHz under the 1.1V supply. The VCO's phase noise is - 86.2dBc/Hz@1MHz at 10GHz with 8.2mW power consumption.

A 10–60 Gb/s wireline transmitter with a 4-tap multiple-multiplexer (MUX) based feed-forward equalization (FFE) is presented. It adopted a novel 4:1 MUX to increase the bandwidth of the final seiralizing stage. Simulation result shows that the proposed 4:1 MUX operates over a wide range of data rate between 10 and 60 Gb/s. Designed in 65 nm CMOS technology, the transmitter exhibits a low jitter of 6.1 ps after a 17 dB loss channel at 60Gb/s.