Search

This paper proposes a 2.4 GHz ultra-low power pseudo-backscatter modulator with an integrated directional coupler for wireless sensor network applications. In order to improve the performance of backscatter modulator for multilevel modulation, an integrated directional coupler is employed to isolate the radio frequency carrier wave from the modulated signal. As a result, the carrier wave can be modulated in radio frequency domain independently without being affected by reflection coefficient of a conventional backscatter modulator. For further reducing power dissipation, the modulator only employs buffers for output and implements modulation by passive circuits. The proposed modulator is demonstrated in a standard 40 nm CMOS 1P10M process and it achieves 64-QAM modulation at 3 Mb/s data rate by consuming only 43.2 μW with a supply voltage of 0.8 V.

In this paper, a novel combinational access topology of Tunnel FET (TFET) SRAM is proposed for ultra-Low Power applications. Since forward p-i-n current of TFET could cause serious damage to SRAM circuit performance, the proposed topology can avoid the forward bias applied to the p-i-n junction, thus increasing SRAM cell read and hold static noise margin (SNM) and decreasing its static power consumption dramatically. At 0.6 V supply voltage, the combinational access TFET SRAM topology presents 26% hold SNM larger than traditional TFET SRAM topologies, 8 orders of magnitude lower static power consumption, and 2 order of magnitude lower power delay product, demonstrating its great potential for ultra-low power applications.

A 12-bit 2.5GHz digital-to-time converter (DTC) for high resolution and high linearity applications is presented in this paper. The DTC is segmented into a 4-bit coarse stage and an 8-bit fine stage. The proposed fine stage utilizes parasitic-insensitive charge-based (PICB) phase interpolator (PI) with significant improvement in linearity. The PICB PI outputs 50% duty cycle differential clock and its performance is insensitive to parasitic effect. The DTC is designed in 40nm CMOS technology and consumes 7.1mW with a 1.1-V supply voltage. Simulation results show that the peak integral nonlinearity and differential nonlinearity are 0.37ps and 0.085ps, respectively.

This paper presents a low power SAW-less 2.4-GHz receiver for short-range communications. To ensure sufficient out-of-band (OOB) linearity for SoC existence, a LC matched series N-path filter based receiver topology is proposed. The radio frequency input is followed by the LC matched series N-path filter, which provides sufficient ultimate rejection when consuming less power than conventional N-path filters. An on-chip inductor and a capacitor are utilized to achieve input matching and improve the NF. Implemented in TSMC 40nm LP process, the chip occupies an active area of 0.312 mm2. Simulation results show that the receiver consumes 2.2 mW from 1.1V supply voltage with a NF of 6.3 dB (with the on-chip inductor) and a voltage gain of 38.4 dB. The baseband achieves a third order filtering response with 1.5 MHz bandwidth. The OOB 1-dB compression point is +7 dBm and the OOB IIP3 is +22 dBm.