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In this paper, the bias-dependent parasitic capacitance of Gate Engineered GAA SiNW MOSFET is investigated in terms of gate capacitance which take into account both gate to source and gate to drain capacitance. Results depict substantial reduction in parasitic capacitance of gate engineered SiNW MOSFET in comparison to conventional SiNW. Further, RF Figure of Merits (FOMs) has also been observed and it is found that GEWE-SiNW exhibit 8.5%, 14% improvement in fT and TFP respectively compared to SiNW MOSFET, thus provide its efficacy for switching applications such as low power CMOS logic gates and wireless/mobile applications. In addition, the impact of metal workfunction engineering has also been observed to examine the detailed knowledge of device.

In this work, we investigated the effect of the gate stack and high-ĸ gate spacers on the digital and analog performance of a lightly doped n-type Si channel Junctionless Rectangular Gate All Around (JL-Re-GAA) FinFET. Different digital and analog parameters, for instance, drain current (I d ), leakage current (I off ), switching ratio (I on /I off ), subthreshold swing (SS), transconductance (g m ), output conductance (g d ), transconductance generation factor (TGF), intrinsic gain (A v ), early voltage (V EA ) have been analyzed. From the simulated results obtained, we have found that the use of gate stack and high-ĸ gate spacers remarkably improves the digital and analog figures of merits (FOMs) of the device. Thus, the JL-Re-GAA FinFET structure with high-k gate spacers and gate stack can be considered as a suitable candidate in digital and analog circuit applications.

In the present day, metallic oxide semiconductor field-effect transistor-based bio-sensors have been frequently used for various purposes due to their low cost and other properties. In this work, high-k Gate-Stack gate-all-around junctionless Silicon Nanowire FET (SiNWFET) is proposed for neutral biomolecule species detection and enhanced the device performance by introduced gate stack and high metal gate work-function. In particular, neutral biomolecule species like Streptavidin, Uricase, APTES, Protein and ChO x are considered in our study. Subthreshold slope, drain induced barrier lowering (DIBL), leakage current, transconductance, and shifting threshold voltage were considered for study the bio-sensor response. Effect of cavity thickness, cavity length, High-k dielectric thickness, and its length on the detection of the device has also become examined. The results in gate stack junctionless gate all around SiNWFET shows better performance in terms of DIBL, transconductance, leakage current, I ON /I OFF ratio and subthreshold slope. The high-k dielectric oxide (HfO 2 ) has been identified for chemical compatibility and thermal stability properties on metal oxide semiconductor transistor as a gate oxide to mitigate the gate tunneling current and short channel effects.

In this work, we proposed and investigated the performance features of a hetero-material junctionless tunnel field-effect transistor (HM-JLTFET) by incorporating -compound semiconducting materials, InAs having low work function, in the source section and GaAs having higher work function, in the channel and drain sections, respectively. The transfer characteristics, subthreshold slope, leakage current, and current switching ratio of the proposed device are also compared with the conventional TFET device having the same dimensions as that of HM-JLTFET. The simulated results reflect the capability of the proposed device to suppress the performance degradation factors like leakage current and power consumption along with improving the current driving capability and fast switching at low gate voltage.

Work presented in this paper reports the impact of graded AlGaN back-barrier on the linearity performance of lattice-matched InAlN/AlN/GaN recess gate device. Specifically, a comparison is made on the linearity of the proposed device with and without a graded back barrier layer. Various device performance matrices namely transconductance (gm) and its higher-order derivatives, second and third-order voltage intercept point (VIP2, VIP3), 3rd order input intercept point (IIP3), 3rd inter-modulation distortion (IMD3) and 1-dB compression point have been investigated and discussed for the proposed device architecture. Results obtained from TCAD simulation of the proposed device confirms that by using graded back-barrier the linearity performance matrices of the device are improved, which further shows that the proposed device is also suitable for wireless applications.