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Today's consumers are looking for powerful, multifunctional electronic devices with unprecedented performance and speed, yet small, thin and low cost. This creates complex technology and manufacturing challenges for semiconductor companies as they look for new ways to achieve greater performance and functionality in a small, thin, low cost device. JCET is an industry leader in Wafer Level Packaging (WLP) technology, providing a comprehensive portfolio of WLP solutions including Fan-in Wafer Level Packaging (FIWLP), Fan-out Wafer Level Packaging (FOWLP) and Integrated Passive Devices (IPD This paper shares data and results from our labs and those of our technology partners which come from two recent tube technology advances, both show great potential for providing solutions to the issues of imaging small features quickly, faced in the higher end semiconductor manufacturing industry. Metal Jet Technology, in metal jet anode microfocus xray tubes the traditional solid metal anode is replaced with a jet of liquid metal, which acts as the electron-beam target, The metal jet supports higher electron-beam power and can therefore generate higher X-ray flux. The major benefit of the increased power density level for the metal-jet X-ray tube is the possibility to operate with a smaller focal spot, say 5 ?m, to increase image resolution and at the same time acquire the image faster, since the power is 10x higher for same spot size. Which means that a 5μm spot on a Metal Jet can tolerate approximately 5x higher power compared to a 10μm spot on a tube with a traditional solid filament This technology delivers one of the smallest and most intensive X-ray beams of any Xray source to meet the ever-increasing technology demands, including wafer level package inspection. Nano Tube Technology This enables industry-leading resolution in geometric magnification, the Nano tube is based on advanced electron optics and the latest tungsten-diamond transmission target technology. Automatic e-beam focusing, and astigmatism correction ensures that the smallest possible, truly round spot is achieved. The Nano tube also has the unique feature of internally measuring and reporting the current spot size. In addition, advanced cooling and thermal design results in extreme stability over time. This enables an unprecedented true resolution of 150 nm lines and spaces. The true round spot of the tube is demonstrated by the highly symmetric images of a ‘Siemens star’ resolution target, the innermost features are 150 nm

Semiconductor and Semi equipment industries expect to see a strong upturn in the next few years, with advanced packaging technologies a significant beneficiary of the markets strength. 5G, AI, Edge Computing, Persistent Memory, Integrated Power Management, and the transition to sub 5nm silicon technology are all driving the need for innovative packaging solutions. These solutions integrate silicon produced with disparate process nodes and deliver maximum performance at optimal cost. Heterogeneous Integration, utilizing a multitude of interconnect methodologies (from Fan-out to Silicon Interposer, to Chiplet), addresses this challenge but requires unique solutions for efficient, cost effective die placement. High speed, high precision multi-die placement, directly and efficiently extracted from a range of different sized wafers, is critical to enable cost effective assembly. This paper looks at the challenges and potential approaches for efficient and cost effective solutions.

High-Performance Computing (HPC) systems increasingly adopt Heterogeneous Integration (HI) technologies that utilize large substrates and high-resolution processes to facilitate die and chiplet. Fan-Out Wafer Level Packaging (FOWLP) and silicon interposers using high-density Redistribution Layers (RDL) can help maximize bandwidth and performance but HI roadmaps require improvements in resolution and lower costs to enable wide adoption of these More-than-Moore technologies. Panel based processes can provide cost advantages compared to wafer processes for fabrication of large interposers and Fan-Out packages. Panel based SiP processes however demand submicron resolution over a large field size and uniform exposure across large panels. To meet these challenges, Canon developed the first lithography exposure system capable of achieving submicron resolution on large panels. The new panel exposure tool targets 0.8 μm design rules and utilizes a new panel handling system and stage that allows processing of panels as large as 515 × 515 mm. The new panel exposure tool is equipped with a UL82 wide-field projection lens with a maximum Numerical Aperture (NA) of 0.24 and offers a 52 × 68 mm exposure field for large device fabrication without stitching adjacent shots. Fine-RDL lithography systems must provide a large Depth-of-Focus (DoF) to maintain pattern fidelity to maximize DoF, the new panel exposure tool applies die-by-die focus and tilt compensation and functions to compensate for panel warpage. Process factors related to DoF include panel flatness and photoresist materials and film uniformity. This paper details test results from a panel exposure system that confirms the feasibility and advantages of submicron panel processes. We also introduce additional challenges related to panel processes including slit-coater uniformity, photo resist materials and panel flatness. We will present data illustrating that new panel exposure tool can provide excellent resolution across large exposure fields on panels to enable HI innovation.

What approaches are available for the flip of devices prior to die bond when the top wafer surface cannot be touched? Conventional 180 degree flip on a chip by chip basis during the die sort process requires rubber vacuum pick-up tools to touch both the top and bottom surfaces of device during the required transfers from one pick-up tool to another. However, for a growing number of applications ranging from medical devices, imaging sensors, MEMS, and bumped die used in flip chip applications, touching the sensitive top surface of a device is not desirable, while the need to flip the device remains. Factors to be evaluated in seeking a successful invert process without top surface contact include throughput, wear resistance of tooling, device and tooling material properties, and risk for top surface damage (yield). A pick and place process using an edge gripper instead of vacuum pick-up tip allowed for no contact of device surface but did not provide a robust device flip process due to imprecise device positioning. However, a non-surface contact approach to protect surface features was able to be achieved by using a radius/channel style pick-up tool to pick the die from the wafer and deposit onto a die inverter arm with vacuum surface contact pick-up tool to hold the device in place from the bottom with vacuum. This arm then rotated 180 degrees to place the device into a second radius/channel style pick-up tool, with the tool touching two of the top edges only. Based on the radius design of the channel style tools, the die protruded past the face of the tool, allowing it to be repicked by the main pick-up tool and then subsequently placed to the output. This non-contact approach was found to successfully protect the device surface during the flip. Future research will focus on improving precision of edge grippers so they may also be a potential solution, as well as the testing of the radius/channel pick-up tip approach for applicability with thin devices.

With the economics of transistor scaling no longer universally applicable, the semiconductor industry is turning to innovative packaging technologies to support system scaling and functionality demands while achieving lower system cost. However, high-density packages such as fan-out wafer-level packaging (FOWLP) bring design challenges that traditional organic laminate processes and design tools struggle with and often fail to satisfy. In this paper, we address the challenges that FOWLP and similar high-density advanced packaging (HDAP) technologies bring to designers, outsourced semiconductor assembly and test (OSAT) suppliers, and foundries, and explain why traditional design processes, flows and even design tools struggle and often fail to achieve high-volume production. We discuss the innovative processes and design techniques that must be adopted not just to comply with design requirements, but to do so in a reliable, productive way to achieve high-quality results that meet manufacturing volume yield expectations. We discuss the processes and design flow Mentor developed through partnerships with leading foundries and OSATs, and how they are being used to drive high-volume production.

Wafer level encapsulation has become increasingly important to build up components for mobile and high-performance computing applications. Ranging from system-in-package and antenna modules to high band-width memory device, many of those wafer-level applications demand new features from encapsulant materials. Besides to provide mechanical protection, new wafer-level encapsulants are preferred to bring in extra features: a) reducing package warpage during wafer-level processing; b) being EU REACH compliant, c) showing excellent flowability for trench-fill or gap-fill. In our new material development, these new features can be achieved in a new type of filled epoxy system. The new class of encapsulants maintains high glass transition temperature (Tg), at the same level of typical semiconductor encapsulants, while demonstrating low-warpage during the wafer-level process, an estimation of more than 50% improvement from typical encapsulants. Owing to the use of fine fillers and new resin chemistry, fine gap-filling is possible. Combination of low-warpage and good flowability allows us to serve better in wafer-level applications. Some case studies will be discussed, including: 1) using liquid compression molding (LCM) process to encapsulate the wafers that have built-in trench-gaps, fine-gaps, or solder-bumps. 2) using stencil printing process to encapsulate trenched wafers. In both process routes, low-warpage, void-free gap-fill can be achieved from the packages. Moreover, the encapsulated test-vehicles passed JEDEC MSL-1 reliability conditions. The results demonstrated that this new wafer-level encapsulants have the potential to meet the growing demands from various wafer-level applications.

Compression molding was developed and introduced by Towa in the early 2000s.Over the years, TOWA has continued to improve and enhance the performance and quality of compression molding and, as a result, it has been adopted for complex packaging solutions, especially those requiring low pressure or very thin molded packages. The ever-increasing demand for integration of different technologies and smaller and thinner footprint continues to march forward. These demands challenge mold compression technology to be further expanded and innovated to address even more complicated packaging requirements such as multi-die in large panel format. In parallel, quality and reliability while meeting these challenges for FOWLP in large panel are also considered in this paper. At present, FOWLP has been targeted for high-end products such as High-Performance Computing (HPC)/ Artificial Intelligence (AI) products using RDL-first / high-precision flip chip bonding process with thinning lines and increasing number of IOs. Furthermore, FO-PLP has become a low-end product target, and chip-first cost reduction is in progress. This paper will discuss the concerns & solutions created by compression molding for panelization to address its growing demand. Compression molding is also discussed as a solution to MUF (Mold Under-fill) associated with flip chip bonding due to the use of a degassing process that employs a highly airtight and high vacuum system, and the ability to dispense resin to the full molding area to suppressthe XY flow of resin during molding. In addition, since the structure is such that the force of the press is directly transmitted to the resin, the range of applicable pressure is wide and it is very effective especially for low pressure molding and particularly for fragile elements and ultra-thin interposers. These characteristics are very effective in the RDL-first process by providing a redistribution layer on the carrier, and helping in the suppression of warpage.

In the next few years, advanced process technologies in advanced packaging fabs will migrate rapidly to reduction lithography to achieve 2/2 RDL and beyond. Reticle enhancement techniques, such as Optical Proximity Correction (OPC) may be required in multiple reticle layers to provide sufficient process latitude for high volume manufacturing. However, a challenge in the manufacturing of OPC reticles is the lack of a precise specifications for defect inspection with respect to the printability on wafers [1]. In this paper, the printability of reticle defects for 2/2 micrometers Redistribution Layer (RDL) design rule are studied via i-line resist process. The reticle defect printability is determined by considering the wafer process critical dimension (CD) variability. In the experiment, an i-line 2x reduction stepper with 0.1 NA imaging lens was used to expose the programmed defect reticle. The resist CD response to the reticle defect area is measured under a variety of process conditions, i.e., different exposure dose or focusThe programmed defect reticles consisted of both Clear and Dark Field polarities comprising of 2/2 design rules will be used for the printability study. Defects such as intrusions and protrusions at various sizes on RDL patterns, have been characterized. Defect disposition comparing reticle to designed programmed defects to those without will be shown as well as the impact of the defect on patterning performance. Finally, the allowable reticle defect requirement is assessed where the printable reticle defect size is tied to the wafer process specifications and the actual wafer process CD controllability. The influence of the reticle manufacturing processes on wafer patterning performance is examined. Through this comparison, insights into target specifications (MTT, CDU, defects) for advanced RDL reticles can be derived while balancing cost tradeoffs.

Moving from monolithic scaling to the second (2D) and to the third dimension (3D) is becoming increasingly important within industry. In the last years heterogeneous and chiplet integration, utilizing advanced packaging technologies, has increased in complexity as well as in variability. Higher performance, wider bandwidth and lower power consumption and space requirements drive the approach toward 3D integration, whereas the need of finer RDL line/spacing as well as smaller μ-bumps and μ-pillars critical dimension tighten integration design rules at the package and substrate level. Individual chiplet's I/O bumps and interconnects pitch scaling nowadays moves towards 2/2μm L/S. Although the flexible re-integration of larger dies from smaller chiplets, from various technology nodes to partitioned dies has shown numerous advantages over monolithic SoC technologies with larger freedom of design, this approach shifts the complexity into the integration and with it into the lithographic patterning processes. In this work a profound evaluation of common advanced packaging high resolution, thin and thick resists for RDL & μ-bump/μ-pillar manufacturing is presented, utilizing maskless exposure to demonstrate its patterning performance. Resolution tests, focal position & exposure matrices, including resist sidewall profiles are discussed in view of the 2/2μm L/S requirements for heterogeneous integration. Furthermore, the high-speed digital processing meets the needs for design flexibility and scalability for a wide range of packaging technologies by enabling both, die- and wafer-level designs, fast tape-out changes together with sub-μm adaptability.

For a novel packaging application, a method is needed to bond silicon chips on a wafer surface. One of the main requirements is a comparably thin and structurable adhesive layer. The adhesive layer has to have a thickness of approximately 10 to 20 μm and is required to cover the edges of the silicon die. As this application is quite unique, thorough research has been done to identify applicable materials and processes. Common technologies like die bonding, pin transfer, jetting etc. cannot be used as the adhesive volume has to be controlled very precise and the dimensions of the adhesive bond are too coarse for the application. The desired thickness of the adhesion layer can only be achieved using photostructurable materials. A parameter analysis has been done in order to determine applicability of the photostructurable material as an adhesive layer. Therefore, die bonding temperature and bonding pressure have been varied. The influence of the parameter variation has been demonstrated using die shear testing and cross sectional imaging. Two geometrical variations of the adhesive layer are compared. A sufficient parameter set could be identified using this approach.

Panel-level packaging such as fan-out wafer-level packaging (FOWLP) has been a promising technology for a number of years now, primarily as a means of packaging semiconductor devices containing interconnect densities that exceed the capabilities of standard wafer-level chipscale packaging (WLCSP). One of the historical barriers to the broad adoption of panel-level packaging is the yield loss associated with “die drift”-die that shift from their designed nominal positions within each package during the manufacturing process. To break through this barrier, we introduce a novel die drift patterning technology that recognizes and adjusts for die drift, making “design during manufacturing” feasible and practical. However, both panel-level packaging and the die drift patterning methodology introduce physical verification challenges that are unfamiliar to most package designers. Panel-level packaging uses a GDSII or OASIS format for the package design, similar to integrated circuit (IC) design databases. Although design rule checking (DRC) is normally run on each individual unit GDSII file, the Die drift patterning process must also be simulated on a complete panel as one overall GDSII mask. This panel GDSII mask includes unique characteristics, with typically thousands of units requiring concurrent verification. The process is substantially more challenging than a classic unit design, where many repetitive GDSII cells exist within a hierarchy that can be used by the verification tools to improve runtimes. Deca collaborated with Mentor, a Siemens business (Mentor) to optimize physical verification for this panel GDSII mask verification. Together, they worked to identify operational impediments and implement optimizations to the verification toolsuite that enabled the platform to support verification of the die drift patterning technology for M-Series fan-out panel level packaging, while also achieving a reasonable turnaround time (TAT) for panel verification. This optimization utilizes both CPU scaling capabilities and a novel computational approach that accounts for the unique characteristics of a die drift patterning panel-level GDSII mask.

In principle there exists a large variety of compositions for oxide glasses. Also a variety of hot forming processes is present for glasses, which allows near end shape processing. In particular thin glasses, directly drawn from a melt, are of interest as a substrate material for packaging of electronics with heterogeneous integration. One main reason seems to be economic manufacturing methods but also mechanic properties like stiffness, correlating to relatively large Youngs moduli, which is the basis for accurate manufacturing with single digit micrometer accuracy. The thermal expansion of glasses can in principle be tailored in a range from 2 ppm/K–12 ppm/K depending on the needs of particular applications. Structuring of glasses either with vias for IC packaging or in combination with cut-outs for fan-out embedding of active and passive components in the substrate layer are possible. Structuring methods which allow millions of vias and thousands of cut-outs in panel level formats are discussed. An efficient and economic metallization process with good adhesion and good electrical performance is a further step for commercializing structured glasses into packaging applications. High frequency applications like inclusion of antenna in package or high-speed digital applications with Gbit/s data rates give further demands on the properties of such structured glasses. In the current work we review the status of glasses for wafer- and panel level packaging. Glasses are available in a large variety; focusing and industrial standardization will speed up industrial readiness of glasses for electronic packaging.

This paper intends to provide insight into the complexities of processing large panel format for Fan-out. It explicitly tackles handling and thermal treatment during the thermal debonding process, which is the method of separating the molded Fan-out panel from the metal plate carrier bonded by a thermal sensitive double-sided tape. Fan-out encounters two prevalent issues inherent to the structure of the package; die-shift and warpage. Both will be covered and have been taken into account in defining the correct process flow and control of panel-level thermal debonding. The handling mechanism of the panel will play a significant role in eliminating potential handling-induced factors. Thermal control, on the other hand, is essential to control die shift caused by any thermal introduction. This paper details how mechanical design, handling, and thermal control come into play to ensure that common issues for a Fan-out structure are also addressed in panel-level form. Different panel matrix layout is examined to identify how it reacts with the optimized process flow.

Interconnects are one of the most difficult steps in the manufacturing process, particularly at advanced process nodes with more metal layers to connect, both internally and externally. The Cu damascene process is widely applied in BEOL of IC industry for interconnect formation while conventional Cu electrochemical deposition (ECD) approach is standard process flow in the packaging area. Conventional Cu ECP has low cost but has limitation on the width of line/space, the process cost will dramatically increase for smaller pitches. At same time, the shrinkage of line/space cannot be prevented with device density increasing. The Cu damascene process can easily achieve sub-micron line/space, it is the dominant interconnect technology for advanced semiconductor chip manufacturing. In a traditional process, trenches and via in dielectric layers are filled by ECD of copper followed by chemical mechanical planarization (CMP) for removal of the metal from field areas of the wafer, CMP has been an enabling technology for the use of copper in damascene technology. It has rapidly become one of the most important and widespread processes, also very costly one. For this application and for any similar process sequence, substantial savings are possible if the metal could be deposited in a selective manner and focused primarily into the features of interest rather than following the traditional inefficient approach of depositing a blanket layer. A novel method for selective deposition (Selectroplating®) has been developed and evaluated for several types of metallization applications. This technology is based on a selective chemical modification (SCM) of field areas of a wafer or substrate and can be implemented for either a fill-based integration, such as Cu dual damascene, or an additive process such as plating of wide conductive lines. In either integration, the primary benefit of selective deposition is to prevent metal from being deposited in areas between desired features thus eliminating the need to remove excess bulk in the next step. Cost savings are realized in two ways: 1) less metal is consumed from the plating bath thus extending bath life and lowering the average deposition cost, and 2) substantially less bulk metal must be removed in the subtractive step which lowers the polish or etch time. This improves throughput and further decreases cost.

Thin glass (≤ 200 μm) has ideal properties for electronic packaging and RF applications. In electronic packaging, a smooth, dimensionally stable surface allows high resolution line/space patterning, while through glass via (TGV) technology permits integration in many relevant packaging structures. These capabilities combine with a low loss tangent at microwave frequencies and robustness to temperature and humidity to yield high performance for RF applications. In this paper we discuss a thin glass handling solution coupled with recent innovations that give glass an entry point into these applications at large scale using existing fabrication infrastructure. Our new polymer-free bonding process allows glass to be temporarily bonded to a handle such as silicon or other glass substrates. The Viaffirm™ bonding material is non-outgassing and capable of handling temperatures in excess of 400°C while remaining temporary. When silicon is used as the handle, the opacity and form factor of the silicon substrate means that the resulting bonded stack is compatible with existing silicon processing equipment. We discuss the properties of our bonding system including temperature performance, tunability of the bond energy for different applications, and approaches to debonding. We also describe the formation and metallization of TGVs utilizing our proprietary process. When using a silicon wafer as the handle substrate, vias in the glass terminate on the silicon and are thus comparable to blind vias in silicon. We discuss the ability to make tapered TGVs while tuning their size and via profile, as well as results in metallization to produce fully filled, void free vias using a range of seed and plating approaches.

Glass is not a new material for Wafer-Level Packaging (WLP) applications and technologies, however, its use is still very limited. Despite its low material cost and incredibly interesting properties, traditional glass microprocessing technologies inevitably increase its cost while negatively affecting the characteristics of glass that made it initially interesting. Laser Induced Deep Etching (LIDE®) is a glass processing technology, developed by LPKF Laser & Electronics [1], that enables highly precise and reliable micro featuring of glass. After processing, the glass is completely defect-free (no cracks, induced thermal stress, etc.) and retains all of its properties. LIDE consists of a two-step process: i) a maskless, direct-writing laser process that only requires a single pulse to modify the whole glass thickness, and ii) a wet etching process done in batch. In summary, this is an incredibly economical technology capable of bringing new life to glass for microelectronics and enabling its full potential for WLP applications. In this work, we will show how LIDE unlocks the use of glass for RF applications by taking full advantage of fused silica's low transmission loss and by enabling the creation of metallized paths in glass connected to through glass vias (TGV). We will also present high aspect-ratio glass interposers for more affordable 2.5D architectures. The formation of spacer wafers with high-accuracy openings of any shape, the production of capping wafers with anisotropically-etched straight sidewalls that significantly increase their die density, the use of glass springs for high precision passive die alignment features, and high throughput and quality dicing/singulation of glass wafers will also be introduced. Laser Induced Deep Etching (LIDE®) is a glass processing technology, developed by LPKF Laser & Electronics [1], that enables highly precise and reliable micro featuring of glass. After processing, the glass is completely defect-free (no cracks, induced thermal stress, etc.) and retains all of its properties. LIDE consists of a two-step process: i) a maskless, direct-writing laser process that only requires a single pulse to modify the whole glass thickness, and ii) a wet etching process done in batch. In summary, this is an incredibly economical technology capable of bringing new life to glass for microelectronics and enabling its full potential for WLP applications. In this work, we will show how LIDE unlocks the use of glass for RF applications by taking full advantage of fused silica's low transmission loss and by enabling the creation of metallized paths in glass connected to through glass vias (TGV). We will also present high aspect-ratio glass interposers for more affordable 2.5D architectures. The formation of spacer wafers with high-accuracy openings of any shape, the production of capping wafers with anisotropically -etched straight sidewalls that significantly increase their die density, the use of glass springs for high precision passive die alignment features, and high throughput and quality dicing/singulation of glass wafers will also be introduced. In this work, we will show how LIDE unlocks the use of glass for RF applications by taking full advantage of fused silica's low transmission loss and by enabling the creation of metallized paths in glass connected to through glass vias (TGV). We will also present high aspect-ratio glass interposers for more affordable 2.5D architectures. The formation of spacer wafers with high-accuracy openings of any shape, the production of capping wafers with anisotropically -etched straight sidewalls that significantly increase their die density, the use of glass springs for high precision passive die alignment features, and high throughput and quality dicing/singulation of glass wafers will also be introduced.

A novel hydrogen activation technology based on activated hydrogen or electron attachment (EA) is developed for fluxless soldering at ambient pressure and normal soldering temperature. The technology has a potential to be used for a list of applications in the electronics packaging industry and recent work by a joint effort between Air Products and Sikama International on alpha trials of a production-scale furnace for flux-free wafer bump reflow based on electron attachment (EA).

Advanced packages are necessary to cope with the requirements of 5G and radar technologies with 60 GHz and beyond. For proper RF design with rising package technology requirements demands for usage of predefined structures with predefined layout elements, manufactured and measured elements. This paper deals with an approach to have such elements available to build advanced types of packages in shorter time compared to classical approaches. The approach is a general approach but it is demonstrated with an advanced two-level package-on-package technology with a leading-edge IC technology. It is also used explain the build-up of a construction kit of RF -blocks from the design phase of test structures up to measurement of such structures, qualification and model building. From the test structure more general structures can be derived and used in the design of future 5G applications. This enables better time-to-market, reduces cost and provides higher design validation in terms of first time right.

Various structures and processes for Fan-Out Wafer Level Package (FOWLP) have already been proposed and developed by many companies. We are also one of them and provide new concept FOWLP technology called RISPAC. Our possesses LSI mass production capability; its LSI manufacturing, assembly and test technologies including WLCSP. Based on those technological backgrounds, the substrate material, substrate size, package structure, and process for FOWLP are determined. Our FOWLP technology targets the Low-Density application field which has relatively small number of pins and small package size. The advantage of applying FOWLP can be obtained even in the field of Low-Density applications. In mean time, however, FOWLP for Low-Density applications requires low cost manufacturing in comparison to the conventional packages. The important points of low cost manufacturing are; 1. Number of parts to be taken from a substrate, 2. Production volume, and 3. Production leveling. For this production leveling, it is necessary to possess FOWLP technology complying customers' requests and have enough product portfolio. To comply with the customers' requests, Our FOWLP technology offers “Resin body type” and “Silicon body type.” In particular, the silicon body type FOWLP is developed utilizing the rigidity of the silicon. This enables the ultra -small and ultra-thin dies to be mounted on a small and thin package. This package is achieved without de-bonding technology; by forming Cu interconnect, internal terminals, and external terminals on the three-dimensional structure by electroplating. Then, the resin sealing and resin grinding are conducted. Our FOWLP technology, the silicon body type RDL-1st FOWLP, was able to materialize the required performance and reliability.

The current study aims at presenting a cost-effective, facile and novel interconnection approach that employs a unique solder ball jetting process (SB2) for stack formations. Conventional methodologies for bridging boards, chips or filling VIAs can be substituted by a solder ball stacking process. In the SB2 process, a bond-head singulates solder spheres which are then liquefied by laser energy and expelled onto a target using nitrogen pressure. Multiple solder droplets could be dispensed at the same location before subsequent translocation of the bond-head. Continued jetting outlined herein could be used to form single or multiple columns (colonnade), or even fill VIA structures. The challenge is to select a parametric window which prevents disintegration of solder stacks at the interface of boards or chips due to parasitic air inclusions or other factors [1]. The process window for three different stacks of solder spheres with varying diameters and aspect ratios (> > 5) are presented and discussed in this work. This work highlights possible combinations of solder stack configurations regarding the size and number of solder balls per stack and the resulting geometrical characteristics. The metallurgical properties of the solder interface were inspected by cross sectional analysis and X-ray. The mechanical strength and corresponding fracture modes were analyzed with a shear test unit and an optical microscope. The vertical offsets associated with column heights were examined with a 3D profilometer. An FEM simulation was performed, confirming and supplementing the experimental findings. Test vehicles pertaining to board-to-board or chip to chip connections using solder ball stacking are demonstrated. As an evaluation material, Si Chips with AlNiAu metallic pads were populated by SAC_305 (Sn 96.5%, Ag 3.0%, Cu 0.5%) stacked solder ball columns. The chip-to-chip assembly was accomplished additionally using a laser-assisted bonding process (LAB). To demonstrate the wide range of applicability and opportunities for column design, low melting-point solder spheres were placed on the corresponding chip to form a solder interface with the pre-processed columns/stacks during the flip-chip process. The ensuing colonnade hybridswere used to support conventional bonding in standard reflow ovens. Finally, future prospects of intended reliability and stability studies are elucidated as well as the opportunity to use this process technique for filling VIAs.

As faster data processing and communication gets more demanded for Data Center/Cloud, HPC (High Performance Computing), AI (Artificial Intelligence) accelerator and Network markets, HBM (High Bandwidth Memory) becomes main memory type to meet the required bandwidth performance. HBM integration with logic dies in a system level has been developed on 2.5D SiP (System in Package) Platform with Si Interposer having TSV (Through Silicon Vias) of which fabrication cost is rather high. Therefore, as the low cost solution, alternative 2.5D SiP Platform approaches such as Organic Interposer using Redistribution Layer (RDL) and Glass Interposer have recently been reported. In this paper, RDL Interposer package with 4 HBM and 1 logic is demonstrated as 2.5D package platform based on RDL-First Fan-out Wafer Level Package (FOWLP). The effect of RDL design factors on electrical performances is investigated using the eye diagram method and fine pitch multi-layer RDL structure (2um L/S RDL, 4 Layers) is designed accordingly. Fine pitch RDL process is established followed by the wafer level and unit level assembly processes and RDL Interposer package is confirmed to meet all the reliability requirements.

300mm carrier wafer for Fan-Out Wafer Level Packaging (FOWLP), is currently the mainstream format used for PMICs, RF and other single die applications. As volume of these devices continue to ramp up, the 300mm medium used for Fan-Out processing continues to stay the same. The need for migrating to panel sizes larger than 300mm becomes a necessity to lower down costs and handle higher volumes. The fastest adoption of Fan-Out technology is now in 5G, automotive and healthcare. Traditional applications such as audio codecs, PMICs, microcontroller units (MCU) and radio frequency (RF) continue to use Fan-Out Wafer Level Packaging (FOWLP) as an alternative to Wafer Level Chip Scale packaging (WLCSP) due to its 5 -sided or 6-sided die protection. As Fan Out packaging becomes mainstream and to get broader adoption of Fan-Out, the need for driving down the cost continues to be at the forefront of Fan-Out suppliers. 600mm × 600mm format utilized in this study leverages existing backend processing equipment used on 200mm and 300mm wafers for cost savings. Utilizing existing equipment would enable the panel to be singulated into 4 × 300mm or 9 × 200mm square segments to enable probe testing. Coupling the 6-sided die protection process (M-Series) with 600mm × 600mm panel level processing paves the way for innovative methods for Fan-Out processing. New photolithography processing utilizing laser direct imaging (Adaptive Patterning ™) to auto scale for die shift mitigation, is heavily dependent on segmentation of the panel. In this instance, the 600mm panel is either segmented into 4 × 300mm, 9 × 200mm or l×600mm for Photolithography steps. Depending on the number of fiducials used during the photolithography steps, capital expenditure and exposure accuracy would be highly dependent on the segmentation chosen. In addition, new metrology tools and panel warpage management will need to be considered for quality assurance. This paper will present a case study of utilizing 600mm × 600mm panel size to process a single die with 6-sided die protection (M-Series). Considerations for repassivation, redistribution layer and solder ball placement will be discussed. Challenges pertaining to large panel processing through the repassivation and redistribution layer will be presented, panel level inspection considerations post mold cure, reliability considerations and future of 600mm × 600mm panel level processing for 6-sided die protection will be summarized.