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The impact of cell size and JFET width reduction on static and dynamic device characteristics is investigated in 1.2-kV-class Schottky barrier diode (SBD)-embedded SiC metal–oxide–semiconductor field effect transistors (MOSFETs). We compare a conventional SBD-embedded MOSFET with improved SBD-embedded MOSFETs with smaller cell pitch and JFET width than the conventional SBD-embedded SiC MOSFET. The optimized SBD-embedded SiC MOSFETs achieve 39% lower on-resistance and 16% lower switching energy loss compared with the conventional design. We also investigate the tradeoff between R on A and short-circuit withstand time (t SC ). Although R on A reduction generally causes a decrease in short circuit withstand capability and reverse conduction capability, we demonstrate that the optimized SBD-embedded SiC MOSFETs have a lower forward voltage drop and short circuit withstand capability. These results show that it is possible to simultaneously reduce R on A and improve t SC with adequate optimization.

In the SBD-embedded SiC MOSFET, the operation of the parasitic PN diode that causes degradation of forward voltage of the diode is suppressed by the incorporated SBD. The aim of this study is to improve the maximum current at which the parasitic PN diode does not operate (I umax ). We confirmed the limitation of the existing equivalent circuit model used as a guideline to improve I umax , and then developed a new circuit model. In addition, a new guideline to improve I umax has been derived based on the equivalent circuit model. Utilizing this guideline, we have tried to improve I umax of 3.3 kV SBD-embedded SiC MOSFET experimentally. I umax at 200°C has been improved to 4.72 times that of the conventional device. Though it has been known that I umax decreases with temperature, this significant improvement in I umax is a promising result for future application of SBD-embedded SiC MOSFET above 175°C.