1. Design of SDH Positive/Zero/Negative Justification Circuits Based on FPGA
- Author
-
Zhou Juan Cui and Liao Lin Hu
- Subjects
business.industry ,Computer science ,Reading (computer) ,General Engineering ,Byte ,Gray code ,Set (abstract data type) ,Sampling (signal processing) ,Embedded system ,Routing (electronic design automation) ,business ,Field-programmable gate array ,Computer hardware ,Electronic circuit - Abstract
A successful design which used FPGA to do Positive/Zero/Negative Justification for adapting E1 (2.048Mbit/s) to SDH C-12 is presented. Gray code is adopted to realize the sampling of write pointer in reading clock domain and induct frequency doubling technology to deduct/insert reading clock, and a positioning counting device is set to complete the positioning insert of specified bytes. Asynchronous FIFO and Ping-Pong operation technique are both adopted. The design realizes stimulation, placement and routing under Quartus II 9.0 circumstances. It is a reusable hardware module which increases performance when compared to existing solutions.
- Published
- 2013