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The energy consumption of supercomputers is one of the critical problems for the upcoming Exascale supercomputing era. The awareness of power and energy consumption is required on both software and hardware side. This paper deals with the energy consumption evaluation of the Finite Element Tearing and Interconnect (FETI) based solvers of linear systems, which is an established method for solving real-world engineering problems. We have evaluated the effect of the CPU frequency on the energy consumption of the FETI solver using a linear elasticity 3D cube synthetic benchmark. In this problem, we have evaluated the effect of frequency tuning on the energy consumption of the essential processing kernels of the FETI method. The paper provides results for two types of frequency tuning: (1) static tuning and (2) dynamic tuning. For static tuning experiments, the frequency is set before execution and kept constant during the runtime. For dynamic tuning, the frequency is changed during the program execution to adapt the system to the actual needs of the application. The paper shows that static tuning brings up 12% energy savings when compared to default CPU settings (the highest clock rate). The dynamic tuning improves this further by up to 3%. [ABSTRACT FROM AUTHOR]

This paper describes the VLSI implementation for identification of characteristic parameters of the given ternary pulse compression sequence and also generates the ternary pulse compression sequence for transmission purpose if the characteristic parameter satisfies certain required value. In this paper an efficient VLSI architecture is proposed to calculate the characteristic parameters of the given ternary pulse compression sequence simultaneously or separately. The hardware architectures reported in the literature till now have the capability of identification of only one characteristic parameter of the ternary pulse compression sequence. In this paper an effort is made for proposing an efficient VLSI architecture for identification of the characteristic parameters i.e. merit factor and discrimination of the ternary pulse compression sequence either simultaneously or separately. If the identified characteristic parameter satisfies certain required value then the proposed architecture in this paper automatically generates the ternary pulse compression sequence for transmission purpose. The VLSI architecture is implemented on the Field Programmable Gate Array (FPGA) as it provides the flexibility of reconfigurability and reprogramability. [ABSTRACT FROM AUTHOR]

Aiming at the shortage of existing real-time screen sharing system, a real-time wireless projection system is proposed in this paper. Based on the proposed system, a weight-based frame deletion strategy combined sampling time period and data variation is proposed. By implementing the system on the hardware platform, the results show that the system can achieve good results. The weight-based strategy can improve the service quality, reduce the delay and optimize the real-time customer service system [1]. [ABSTRACT FROM AUTHOR]

The paper presents the approach to modelling of the transport delay using several approximation formulas. The selected approximation of the transport delay is then used in the simple control system model to demonstrate its operation. The aim of the approach is to create the homogeneous system, therefore, hardware representation is discussed. [ABSTRACT FROM AUTHOR]

In Computer Science, the Boolean Satisfiability Problem(SAT) is the problem of determining if there exists an interpretation that satisfies a given Boolean formula. SAT is one of the first problems that was proven to be NP-complete, which is also fundamental to artificial intelligence, algorithm and hardware design. This paper reviews the main algorithms of the SAT solver in recent years, including serial SAT algorithms, parallel SAT algorithms, SAT algorithms based on GPU, and SAT algorithms based on FPGA. The development of SAT is analyzed comprehensively in this paper. Finally, several possible directions for the development of the SAT problem are proposed. [ABSTRACT FROM AUTHOR]

With the advent of the era of big data, amount and importance of data have increased dramatically. SQL database develops in performance and scalability, but more and more companies tend to use NoSQL database as their databases, because NoSQL database has simpler data model and stronger extension capacity than SQL database. Almost all database designers including SQL database and NoSQL database aim to improve performance and ensure availability by reasonable architecture which can reduce the effects of software failures and hardware failures, so that they can provide better experiences for their customers. In this paper, I mainly discuss the architectures of MySQL, MongoDB, and Redis, which are high available and have been deployed in practical application environment, and design a hybrid architecture. [ABSTRACT FROM AUTHOR]

In this paper, it firstly introduces the related knowledge of access control list (ACL) technology, hardware requirements and software configuration. Then it discusses the topological structure of campus network from the perspective of campus network planning as well as demonstrates the application of ACL technology in campus network combined with examples. [ABSTRACT FROM AUTHOR]

Introduces a system design scheme of the telephone dialer based on Arduino, including the design principle, hardware and software design and the experimental results in this paper. The scheme is based on the dual tone multi frequency (DTMF) dialing mode, using the Arduino UNO as the main controller, the serial port send out the telephone number to be dialed, speaker synthesize the voice. [ABSTRACT FROM AUTHOR]

The arrival of hardware accelerators has created a new gold rush to be the first to deliver their promise of high performance for numerical applications. Despite the recent advances in programmability, it is still hard to develop tuned programs that extract all the potential performance promised by the manufacturers. In this paper we remind the community that while this development effort is a noble endeavor, there is a lot of low hanging fruit that can be harvested easily. Picking this low hanging fruit benefits the scientific computing community immediately and prototypes the approach that further optimizations may follow. We demonstrate this by focusing on a widely used set of operations, the level-3 BLAS, targeting the NVIDIA GPUs. [ABSTRACT FROM AUTHOR]

The investigation of the two-phase flow measurement is important in industrial processes investigation. The research of the flow regimes identification has more significance. As a new instrument, virtual instrument combines computer resources, measurement and control hardware, data analysis and graphical user interface software together, which has a wide range of applications in practice. Neural network and LabVIEW are combined and applied in flow regimes identification, which advance the capability and the developing efficiency of the testing system. This paper introduces the software of gas-water two-phase flow regime on line identification based on LabVIEW with the method of neural networks. [ABSTRACT FROM AUTHOR]

Programmability is an important capability that provides flexible computing devices, but is incurs significant performance and power penalties. Performance problems cannot be solved by simply increasing operating frequency while relying on technology improvements for low power. Instead, DSP architectures need to be adapted specifically for low power operation. This paper proposed an architecture that relies on dynamic reconfiguration of hardware resources to implement low-power and programmable processors for DSP applications. This technique has shown to yield at least an order of magnitude of power reduction compared to traditional instruction-based engines for problems in the area of wireless communication. [ABSTRACT FROM AUTHOR]

In this paper HPC architectural characteristics and their impact on application performance and scaling are investigated. Performance data gathered over several generations of very large HPC systems like: ASC Red Storm, ASC Purple, and a large InfiniBand cluster—Red Sky, are analyzed. As the number of cache coherent cores and number of NUMA domains at a compute node keeps increasing, we analyze their impact with a few simple benchmarks and several applications. We present bottlenecks and remedies examining production applications. We conclude with preliminary early-hardware performance data from the ASC Cielo, a petaFLOPS class future capability system. [ABSTRACT FROM AUTHOR]

Analog-to-Digital Converter (A/D) is a critical component of Software Radio (SWR). Various hardware restrictions and errors are limiting SWR’s performance. In this paper the performance of a SWR receiver is evaluated considering A/D’s clipping noise. Significant results are given, in terms of clipping noise, in combination with aperture jitter and quantization error. [ABSTRACT FROM AUTHOR]

This article describes a parallel computational technique to accelerate radial point interpolation method (RPIM)-based meshfree method using graphics hardware. RPIM is one of the meshfree partial differential equation solvers that do not require the mesh structure of the analysis targets. In this paper, a technique for accelerating RPIM using graphics hardware is presented. In the method, the computation process is divided into small processes suitable for processing on the parallel architecture of the graphics hardware in a single instruction multiple data manner. [ABSTRACT FROM AUTHOR]

This paper presents architecture of augmented reality for e-maintenance application. In our case, the aim is not to develop a vision system based on augmented reality concept, but to show the relationship between the different actors in the proposed architecture and to facilitate maintenance of the machine. This architecture allows implementing different scenarios which give to the technician possibilities to intervene on a breakdown device with a distant expert help. Each scenario is established according to machine parameters and technician competences. In our case, a hardware platform is designed to carry out e-maintenance scenarios. An example of e-maintenance scenario is then presented. [ABSTRACT FROM AUTHOR]

In this paper, the adaptive backstepping control with an observer is presented for the class of nonlinear systems. The problem of observability has a practical importance, because certain intern variables are some times inaccessible to measurement or “expensive” to measure. Generally the physical utilization of a sensor is impossible for reasons of implementation or cost, which do not allow the measurement of all the states. We will see how we can start from measurements of inputs and outputs of the process, to reconstruct (we also say to observe), the complex state vector. The subsystem, which carries out this reconstructing, is called the observer. To clarify the approach further, an example of simple pendulum is studied and the results of simulation clearly show the power of this approach. [ABSTRACT FROM AUTHOR]

This paper concerns keystroke dynamics, also partially in the context of touchscreen devices. The authors concentrate on the impact of database quality and propose their algorithm to test database quality issues. The algorithm is used on their own as well as the well-known . Following specific problems were researched: classification accuracy, development of user typing proficiency, time precision during sample acquisition, representativeness of training set, sample length. [ABSTRACT FROM AUTHOR]

Hardware computation of large-scale neural networks models is a challenge in terms of calculation precision, data bandwidth, memory capacity and overall general system performance. Proposed reduced precision computations at Half, Mini and Nibble floating-point formats are dedicated mainly to systems with computational power deficits in order to increase efficiency and to maximize hardware resources utilization. The study examined 10 neural networks models of varying architecture (MLP, NAR) and purposes (fitting, classification, recognition, and prediction). The number representation for all ANN models were downgraded to Half (16-bit), Mini (8 bit) and Nibble (4 bit) floating-point precision. For each reduced precision ANN, statistical estimators such as MAE, MSE and Supremum were calculated. Particular attention was devoted to pattern recognition networks in which object classification skills have been preserved despite an extreme precision reduction (4 bits). In addition, the paper shortly describes ANN bandwidth demands, a reduced precision format development and achieved performance gains. [ABSTRACT FROM AUTHOR]

Reservoir computing is a very recent, neural network inspired unconventional computation technique, where a recurrent nonlinear system is used in conjunction with a linear readout to perform complex calculations, leveraging its inherent internal dynamics. In this paper we show the operation of an optoelectronic reservoir computer in which both the nonlinear recurrent part and the readout layer are implemented in hardware for a speech recognition application. The performance obtained is close to the one of to state-of-the-art digital reservoirs, while the analog architecture opens the way to ultrafast computation. [ABSTRACT FROM AUTHOR]

Jitter is a matter of great concern for high-speed digital designers because of its ability to degrade the overall system performance. Designing a low-jitter and wide-band phase locked loop (PLL) system is of practical importance because of its application in high speed digital systems. This paper experimentally investigates a low-jitter and wide-band dual cascaded PLL system using a single crystal oscillator. The first PLL used in the system employs a voltage-controlled crystal oscillator (VCXO) to eliminate the input jitter whereas the second PLL provides wide bandwidth. Field Programmable Gate Array (FPGA) is used to generate a jittered clock source which is then passed through the proposed system to achieve wide-band and low-jitter signal. Experimental results are presented to validate the proposed technique for different carrier frequencies. [ABSTRACT FROM AUTHOR]

Efforts to build Hi-Tech modern astronomical observatories for viewing space results in unbelievable technological spin offs, because these instruments require not only astronomers but skilled engineers and technicians in electronics, optics, mechanics, computer hardwares and softwares to function. There is need for African National Governments to recognize the intrinsic value of astronomy and its importance as an essential component for technological and economic growth. In this paper we highlight astronomy development in Nigeria, Nigeria's Space initiative and the contribution of astronomy to the success of Nigeria's Space initiative. [ABSTRACT FROM AUTHOR]

The Control System for the Advanced Light Source uses in-house designed IndustryPack (IP) I/O Modules in compact PCI (cPCI) chassis to control instrumentation. Each module consists of digital I/O ports and 16-bit analog I/O interfaced to instrumentation via a cPCI rear I/O card. During the past few years of installed operation, several factors have prompted investigation into the design of a new IP I/O Module. The ADC channels have significant offset drift over periods of days of initial installed operation. An in-situ calibration procedure was developed to address this problem, but it lacks speed and is inconvenient to perform. Digital I/O port limitations have led to increasing amounts of wasted I/O. Fast orbit feedback requires faster ADC sampling and better filtering than the current IP Module offers. This paper discusses the issues related to the current IP I/O Module and the design of a new Double-size IP I/O Module. © 2004 American Institute of Physics [ABSTRACT FROM AUTHOR]

This paper introduces the composition of RFID system, and then analyzes the hardware design and software design systems, and finally summarizes the realization and application of the confidential data management system RFIDbased. [ABSTRACT FROM AUTHOR]

Early science returns in the field of Space Human Life Science will be accomplished onboard the International Space Station (ISS) through the use of the Human Research Facility (HRF). The Human Research Facility is the first facility-class payload that will be integrated into ISS. HRF is a suite of internationally developed hardware basic to the study of the human body’s adaptation to microgravity. This hardware has been, in most cases, procured from commercial vendors and re-packaged for integration into a standard space station payload rack. The efforts to prioritize science needs, station capabilities, research agendas, resources available, and how all these tie into hardware and experiment development will be the focus of this paper. © 2000 American Institute of Physics. [ABSTRACT FROM AUTHOR]

To apply ZigBee technique in smart home circuit design, in the hardware design link of ZigBee node, TI Company's ZigBee wireless communication chip CC2530 was used to complete the design of ZigBee RF module circuit and peripheral circuit. In addition, the function demand and the overall scheme of the intelligent system based on smart home furnishing were proposed. Finally, the smart home system was built by combining ZigBee network and intelligent gateway. The function realization, reliability and power consumption of ZigBee network were tested. The results showed that ZigBee technology was applied to smart home system, making it have some advantages in terms of flexibility, scalability, power consumption and indoor aesthetics. To sum up, the system has high application value. [ABSTRACT FROM AUTHOR]

The Research Computing Center of Lomonosov Moscow State University is developing the Octotron software suite for automatic monitoring and mitigation of emergency situations in supercomputers so as to maximize hardware reliability. The suite is based on a software model of the supercomputer. The model uses a graph to describe the computing system components and their interconnections. One of the most complex components of a supercomputer that needs to be included in the model is its communication network. This work describes the proposed approach for automatically discovering the Ethernet communication network topology in a supercomputer and its description in terms of the Octotron model. This suite automatically detects computing nodes and switches, collects information about them and identifies their interconnections. The application of this approach is demonstrated on the "Lomonosov" and "Lomonosov-2" supercomputers. [ABSTRACT FROM AUTHOR]

Since the evolution of the computer's hardware in the middle of last century, the automatization processes are very productive in fields such as industry, security, engineering and science. In this work a pattern recognition methodology to classified images is presented. Here, the Bessel masks digital image system invariant to position and rotation is utilized to classified gray-scale images. Moreover, by the use of the Fisher's Z distribution the digital system get a 99% confidence level performance. [ABSTRACT FROM AUTHOR]

In the field of ultrasonic imaging, the synthetic aperture techniques are well known due to their ability for obtain images using fewer resources. Initially, these techniques were developed to reduce the cost and complexity of phased array instrumentation. Although these drawbacks have already been overcome, the interest on the synthetic aperture systems has not decayed. The reasons of that are the high image quality achieved with these techniques (images dynamically focused both in emission and reception), and the fact that they are an excellent solution for the design of new high performance instrumentation with a low volume and power consumption, easily integrable in autonomous and embedded systems. Using the coarray as a model of the pulse-echo systems, the present work analyzes experimentally the main synthetic aperture strategies appeared until now, introducing two new proposals (2R-SAFT and nR-SAFT) that allow to improve the quality of the images without increase the hardware complexity of the system. [ABSTRACT FROM AUTHOR]

Today's parallel hardware architectures and computer memory hierarchies enforce revisiting fundamental algorithms which were often designed with algebraic complexity as the main complexity measure and with sequential running time as the main performance counter. This study is devoted to two algorithms of univariate polynomial multiplication; that are independent of the coefficient ring: the plain and the Toom-Cook univariate multiplications. We analyze their cache complexity and report on their parallel implementations in Cilk++ [1]. [ABSTRACT FROM AUTHOR]

FLASH is a highly capable multiphysics multiscale modular extensible code, originally designed for simulating reactive flows. FLASH consists of interoperable modules that can be combined to generate different applications such as simulations of novae, supernovae, X-Ray bursts, galaxy clusters, weakly compressible turbulence, and many other problems in astrophysics and other fields. FLASH has a wide user base, both within and outside the Flash Center, and is regularly used on largest available HPC platforms. With each new platform we encounter a new set of challenges, because the multiscale multiphysics nature of FLASH simulations exercise the machine’s hardware and system software greatly. The increase in the degree of concurrency with each new hardware generation has imposed changes on some of FLASH’s parallel algorithms. The pace of change has accelerated with the move towards petascale, and then to exascale. In this work we present some of our scaling hurdles and their solutions. In addition we discuss a more fundamental transition in the code to incorporate a hybrid shared and distributed memory model in preparation for the future million- to billion-way parallelism. [ABSTRACT FROM AUTHOR]

The requirement of high performance and memory for computer simulations is still growing. Due to hardware constraints like power consumption, heat dissipation and other physical limitations the development trend in high performance computing (HPC) tends to multicore design patterns. As new computational platforms become increasingly more complicated and heterogeneous, there is the need for portable programming models that easily enable the exploitation of these architectures. Additionally, algorithms are needed that are able to match the platform specific requirements and exploit their potential power. This work focuses on the particle-based algorithm Multiparticle Collision Dynamics (MPC) for the calculation of hydrody-namic properties of fluid and flow phenomena. This algorithm has already been ported to Cell Broadband Engine (Cell/BE) by using the high-level programming model Cell Superscalar (CellSs). Performance results of the Cell/BE implementation and a recently developed OpenMP version are presented. Furthermore, the possibilities for porting this application also to GPUs with minor effort are pointed out and a strategy for hybrid implementations to use multiple nodes in a cluster are examined. [ABSTRACT FROM AUTHOR]

We propose a compositional modeling framework for Mixed Reality (MR) software architectures in order to express, simulate and validate formally the real-time properties of such systems. Our approach is first based on a functional decomposition of such systems into generic components. The obtained elements as well as their typical interactions give rise to generic representations in terms of timed automata. A whole application is then obtained as a composition of such defined components. The approach is illustrated on a case study modeled by timed automata synchronizing through channels and including a large number of time constraints. This system has been simulated in UPPAAL and checked against basic behavioral properties. [ABSTRACT FROM AUTHOR]

Over the last 20 years many labs started to use Allison scanners to measure low-energy ion beam emittances. We show that large trajectory angles produce ghost signals due to the impact of the beamlet on the electric deflection plates. The strength of the ghost signal is proportional to the amount of beam entering the scanner. Depending on the ions and their velocity, ghost signals can have the opposite polarity as the main beam signals or the same polarity. These ghost signals are easily overlooked because they partly overlap the real signals, they are mostly below the 1% level, and they are often hidden in the noise. However, they cause significant errors in emittance estimates because they are associated with large trajectory angles. The strength of ghost signals, and the associated errors, can be drastically reduced with a simple modification of the deflection plates. © 2005 American Institute of Physics [ABSTRACT FROM AUTHOR]