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Many successive improvements of the charge pump (CP) principle introduced by Dickson have paved the way to efficient integrated DC-DC converters. One of the most used CP is the bootstrap Dickson CP, or its double version. However, the best achievement is certainly the latched charge pump (LCP). Indeed, as in a Dickson pump, it makes use of pump capacitors in parallel, lowering its sensitivity to parasitic capacitors and allowing high pump gain. As a double structure, it also exhibits a low output voltage ripple. But one of its best advantages is that it only requires a simple two-phase clock and thus less transistors than the bootstrap CP. Yet, few studies have been published on the LCP. Therefore, this paper focuses on the modeling and design of LCPs. It provides the designer with a simple and robust way to quickly design such a pump when it is meant to be loaded with a resistor and has to deliver a steady-state current. Its optimization in terms of silicon area, efficiency or efficiency-to-area ratio is also discussed. It is shown than contrary to all the previous studies on CP optimization, the total area of the pump, i.e. the area of the capacitors but also the area of the switching transistors have to be considered for a better optimization. Experimental results obtained on a 22 V output voltage CP able to deliver 42 μA, designed in a high-voltage 0.35 μm CMOS technology, are also given. [ABSTRACT FROM AUTHOR]

This paper presents the improvement of an existing design-oriented compact model of the 5-contact vertical Hall-effect sensor integrated in CMOS technology. Such a model should facilitate the work of designers, permitting them to simulate the sensor, the biasing and processing electronics together with the same electrical simulator. Focus is put on the main aspects that alter the electrical response of the sensor: modulation of the conduction channel due to the bias-dependent space charge region thickness, saturation of carrier velocity, asymmetries, and effective channel conduction thickness. The model has been achieved with a subtle mix of theoretical considerations, numerical simulations performed with COMSOL Multiphysics and experimental data. The parameters extraction procedure is also discussed. The model has been validated on experimental data gathered from two devices, one fabricated in a low-voltage CMOS technology and the other one in a high-voltage CMOS technology. Then, the model is used in order to study offset issues in VHD with external measurement contacts, i.e. VHD integrated in the shallow N-well of low-voltage technologies, and the way the spinning current technique can be used to suppress this offset. A new spinning-current technique is proposed for such a VHD. The simulation results are in perfect accordance with the analytical study. They pave the way for the design of an optimized readout circuitry that may improve the sensor sensitivity while maintaining a very low offset. [ABSTRACT FROM AUTHOR]

This paper presents the development of a design-oriented compact model of vertical Hall-effect sensors integrated in CMOS technologies. Such a model makes easier the design of integrated Hall systems, permitting designers to co-simulate the Hall sensing element with the biasing and processing electronics thanks to a single electrical simulator. Here focus is put on the electrical behavior, i.e. the resistive behavior of a 5-contact vertical Hall device. The model is based both on theoretical considerations and on FEM numerical simulations performed with COMSOL. The result is a new predictive compact model, written in Verilog-A, with 7 input terminals and 14 parameters, mainly sensor geometrical and technological parameters. These parameters can be easily extracted from measurements carried out on a single sensor. The compact model has been validated by FEM simulations, as well as by comparing its response with experimental results obtained from a vertical Hall device fabricated in a CMOS 0.35 μm technology. The root mean square error of the model with respect to experimental results obtained on a wide range of typical sensor biasing conditions is below 2 %. Such a resistive model opens the way to an efficient, complete compact model of the vertical Hall device, i.e. including the Hall-effect as well as all the second-order galvanomagnetic effects. [ABSTRACT FROM AUTHOR]

A compact model of a cross-shaped horizontal integrated Hall-effect sensor is presented in this paper. Compared to existing models, reliability is improved, especially to simulate systems in which biasing and measurement circuits are not independent. The Hall device model core, already published, is based on a network of six non-linear resistances and four Hall voltage sources, and includes only 11 physical parameters. In this paper, in order to improve model predictivity, four additional parameters have been added to take the offset issue into account. In addition, variations of parameters with temperature are also addressed. The model is implemented in Verilog-A and has been validated through experiments carried out on Hall devices designed in a CMOS 0.35μm technology. The parameters extraction procedure is detailed and the maximum error between simulations and experimental data is less than 1 % for a wide range of biasing currents and temperatures. [ABSTRACT FROM AUTHOR]