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In this study, MOS-Only transimpedance mode filters are proposed. The presented circuits use two capacitors and MOS transistors that operate in saturation mode. The circuits are additional examples contributing to the set of previously published circuit topologies. One of the circuits is chosen and its functionality is verified with simulations. An important aspect of the chosen design is the versatility of filter parameters. Changing the drain currents of MOSFETs makes it possible to adjust the center frequency after production. We performed simulations with the LTSPICE simulation program using 0.18 μm TSMC CMOS technology. Simulation results are found in close agreement with the theoretical results. [ABSTRACT FROM AUTHOR]

This work is a review article that sheds light on the active and passive sensitivities of the active RC filters based on opamp. This work provides a detailed analysis through different filters realization criteria and sensitivity summary tables and quantitative insight by discussing the most significant. However, some are almost forgotten, filters families in the literature over decades. A detailed mathematical analysis for the passive sensitivity to compare the filters' realizations is presented. The concept of dealing between filter design theory and filter design circuit realization is highlighted. Some filters families are chosen from the literature for the analysis. Some detailed specifications tables for each filter family are given. Monte Carlo simulation is carried out on some filters to compare their passive sensitivity. Furthermore, the effect of the active sensitivity of some filters is verified through simulation by adjusting the input common-mode voltage to lower the DC gain of the amplifier. The results of the simulation match with the theoretical analysis and the summary provided in the specifications tables. [ABSTRACT FROM AUTHOR]

In this paper, we present six area-efficient transimpedance type second-order analog filters. There are many applications where the available signal is current, however the necessary signal for further processing is voltage type. For such applications the presented circuits will be a useful solution. The technique employed is called MOS-only technique and to the best of our knowledge this is the first attempt to implement transimpedance type filters with MOS-only technique. Starting from the core circuit biasing is illustrated and the functionality is shown with LT SPICE simulations using TSMC 0.18u technology parameters. From six core circuits one circuit is selected and the design is completed for illustration purpose. [ABSTRACT FROM AUTHOR]

In this paper, plus-type differential voltage current conveyor based two voltage-mode (VM) analog filters with high input impedance properties yielding easy cascadability with other VM circuits are proposed. The first proposed filter can simultaneously provide all the second-order universal filter responses except all-pass one, and employs only grounded passive elements that are canonical in number. The second one can simultaneously realize all the second-order universal filter responses, and includes one floating resistor, one grounded resistor and two grounded capacitors. No passive element matching condition is required for both of the proposed analog filters. However, both of the proposed filters do not have the feature of orthogonal control of angular resonance frequency and quality factor. Many simulations such as AC, transient, Monte Carlo, etc. are performed to denote the performances of both of the proposed analog filters. [ABSTRACT FROM AUTHOR]

This paper presents a 4th-order low-pass continuous-time Diode-RC filter with 24 MHz cut-off frequency. The filter structure is based on the combination of positive (passive) and negative (using cross-coupled MOS transistors) cells to synthesize complex-conjugate-poles pairs. Moreover, the filter is designed and optimized to have high-linearity along all the filter pass-band. The filter exhibits 16 dBm- IIP 3 with 2–3 MHz input tones and 5 dBm- IIP 3 with 23–24 MHz, whereas the current consumption remains limited to 100 μ A from 1.8 V supply voltage. [ABSTRACT FROM AUTHOR]

This paper presents a 28 nm-bulk-CMOS 3rd-order 132 MHz low-pass filter based on an improved Active-gm-RC stage. Challenges related to the design of analog circuits in 28 nm-bulk-CMOS process node are faced, mitigated and exploited by operating at both architecture and circuit design levels. The filter uses a single-opamp two-stage topology where both poles are used for synthesizing a 3rd-order low-pass transfer function. The proposed filter operates from a single 0.9 V supply voltage, consumes 340 µW and performs high linearity (IIP3 = 11.5 dBm at 21 and 22 MHz input tones) and large Signal-to-Noise ratio (58 dB). This enables one of the higher Figure-of-Merit (163.2 dB) with respect to the state-of-the-art. [ABSTRACT FROM AUTHOR]

A new low-voltage, MOSFET-only, third order low-pass filter is proposed. The circuit employs only MOSFETs operating in saturation region. The transconductance gains and the parasitic gate to source capacitances of the MOSFETs represent resistive and capacitive elements of the filter. Using TSMC 0.18 µm technology parameters the circuit is simulated, non-ideal effects have been investigated and dynamic threshold voltage MOS tuning technique has been developed for the filter circuit to suppress the non-idealities. In this tuning technique, bulk terminals of MOS transistors are used to adjust the biasing point of the circuit by changing the threshold voltages of the MOS transistors. This gives the designers more flexibility than conventional tuning methods and allows low voltage operation when several transistors are stacked over each other. The resulting circuit is capable of operation at high frequencies with low power consumption due to the usage of significantly less number of transistors than conventional active block-based filtering circuits. [ABSTRACT FROM AUTHOR]

A novel pseudo differential transconductor for multi-mode analog baseband channel selection filter is presented. The highly linear transconductor is designed based on the dynamic source degeneration and predistortion cancellation technique. Meanwhile, wide tuning range is achieved with the current division technique. An LC ladder third-order Butterworth low-pass filter implemented with transconductors and capacitors was fabricated by TSMC 0.18-μm CMOS process. The results show that the filter can operate with the cutoff frequency ranging from 4 to 20 MHz. The tuning range is wide enough for the specifications of IEEE 802.11a/b/g/n Wireless LANs under the consideration of low power consumption and linearity requirement. The maximum power consumption is 3.61 mA at the cutoff frequency of 20 MHz. [ABSTRACT FROM AUTHOR]

A high-accuracy on-chip auto-calibrating architecture is presented to compensate the process and temperature parameter variations in high-linearity continuous-time filter. The on-chip auto-calibrating architecture consists of a clock generating circuit, a voltage comparator, a digital tuning engine, and an analog integrator with similar time-constants as the tuned filter. Discrete capacitor arrays are utilized to tune filter automatically for preserving a high linearity. A fourth-order RC filter for GNSS receivers is fabricated in 0.18 µm CMOS process to verify the performance of proposed tuning architecture. With adjustment, this filter achieves less than 5 % frequency uncertainty. The whole circuit consumes 5.2 mA under a 1.8 V supply and occupies a die area of 0.55 mm. Both the post-layout simulation and measured results indicate that the auto-calibrating architecture is a useful and adequate solution to compensate the errors caused by factors such as fabrication tolerances, changes in operating conditions, parasitic effects and aging. [ABSTRACT FROM AUTHOR]

In this study, a current-mode dual output low-pass and band-pass filter is presented using only six MOSFET transistors in its core. Transconductances and gate-to-source capacitances of the MOS transistors are employed instead of passive resistors and capacitors. The proposed circuit exhibits important features such as simplicity, low-voltage/power operation, reduced chip area and wide frequency range compared to classical analog circuits that require active elements with large number of transistors. Simulations are performed to verify the theoretical results. [ABSTRACT FROM AUTHOR]