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Though Current Mode Logic has excellent features like higher switching speed and reduced crosstalk due to small output swing, there exists numerous flaws such as static power dissipation, non-suitable for power-down modes and comparably higher design complexity of load resistors. To address the aforementioned worries, this article incorporates a dynamic current mode design approach having active load and controlled current source to configure an improved (2/3) dual modulus prescaler. Simulation results of the proposed circuit using Cadence Virtuoso platform for 90 nm CMOS at 1.2 V supply depict a power consumption of 2.517 mW when driven by a high frequency of 2 GHz. The phase noise and output noise are found to be − 147.001 dBc/Hz and − 181.7 dB at 1 MHz offset while it reads a self-oscillation frequency of 5 GHz. The variation tolerance of the design is proved via 5% skew-based simulation at all corners; whereas the correct functionality at 28 nm UMC justifies its scalability. more...

Tremendous and inescapable application of full adder adds impetus to its optimization till high-end performance. Use of full adder propels the design engineer to unearth various digital circuits, whose implementation otherwise would not be a cakewalk. This paper exhumes finest 3-bit parity checker in terms of power dissipation (PWR) and energy-delay product (EDP) variability. MCML (MOS Current Mode Logic) based implementation is practiced to improvise the circuit. Further, in this treatise, above mentioned 'CNFET-based 3-bit MCML parity checker' (used as full adder) and Transmission Gate based multiplexer is used to implement a novel design of '4-Bit 4-Tube CNFET based ALU' at 16-nm Technology Node. This CNFET-based ALU thus implemented is further compared with its CMOS counterpart. Simulation results establish the superior performance of proposed '4-Bit 4-Tube CNFET-based ALU' in terms of propagation delay (tp) (9.04×), PWR (1.68×), PDP (15.09×) and EDP (136.42×). The exposition establishes that the idea of using a 'CNFET-based 3-bit MCML parity checker' to design a new ALU circuit, i.e., '4-Bit 4-Tube CNFET-based ALU' would provide a gigantic horizon for a design engineer. more...

MCML (MOS Current Mode Logic) based implementation producing fast response and compliment output at the same time gives an impetus to the researcher to replace Bulk CMOS. Moreover, tremendous challenges faced by bulk CMOS at channel lengths below 45 nm induces a need to strive for a technological replacement of silicon in years to come. This introduces a zest in designer's mind to look for competent and novel substances to overcome the shortcoming of existing silicon. The future technology should be capable to deliver fast response, low power operation, scalable to reduced dimensions, and strong towards process variations. Carbon nanotube based technology (CNFET) is one of the reliable and competent alternative because it has most of these desired features and similar operating principle as that of CMOS. And hence, this research article focuses on a relative evaluation of CMOS and CNFET version of 3 bit parity checker at 16-nm technology nodes. The CNFET based 3 bit parity checker is faster (9.75×), it offers improvement in power dissipation (11.93×), improvement in PDP (116.39×), improvement in EDP (1135.76×) compared to CMOS counterpart. Scaling down the device emerges with a challenge of variability, just as power, delay and area, variability also has an impact on performance of the circuit. Technology scaling has significant consequences such as wider variation. This research article also presents variability analysis, in terms of delay (tp) and power-delay product (PDP) for the proposed CNFET based MCML 3 bit Parity checker circuit. Extensive simulation using 16-nm technology node are carried out by loading two nominal copies of 'CNFET based MCML 3 bit Parity checker' (Circuit under Test) at either ends—input and output. This simulation framework supports the high level integration where stand alone operation has no application in the industry. The intent of this research is to investigate the circuit with minimal variability to propagation delay and PDP. The proposed ‘CNFET based MCML 3 bit parity checker’ exhibits improvement in delay (14.01×) and improvement in PDP (242.1×) variability as compared to CMOS counterpart. Thus, the CNFET based implementation emerges out as a robust circuit showing narrower spread in variability analysis against applied VDD. more...

A compact 0.045–2.3 GHz wideband fractional-N frequency synthesizer (FS) for software defined radios (SDR) applications is presented in this paper. Based on a single phase locked loop (PLL) that employs one integrated inductor-capacitor voltage controlled oscillator (VCO), the proposed FS can provide a wide operating frequency range. The VCO adopts an optimized circular inductor to mitigate the phase noise degradation caused by the high VCO gain. The in-band phase noise is optimized by employing current mode logic dividers and true single phase clock dividers. The PLL provides the differential outputs ranging from 2.3 to 4.6 GHz and the 0.045–2.3 GHz quadrature local oscillator signals are generated by the following divider chain. The proposed FS is implemented in TSMC 180 nm RFCMOS process and provides a phase noise performance less than − 116 dBc/Hz at 1 MHz offset. The maximum power consumption is 54 mW. The die size including pads and I/O is 1.92 mm2 with an active core area of 1.13 mm2. This proposed circuit has the great potential for SDR applications. more...

A high-speed, low voltage CMOS current mode logic (CML) latch, that has high input, and output voltage dynamic ranges, is proposed in this paper. The input common-mode voltage, and the output voltage dynamic range behavior are analyzed for the proposed latch and the most common (or typical) latch. Both CML latch structures were designed in a 0.18 $$\upmu$$μm RFCMOS technology with a nominal voltage $$V_{DD}=1.8$$VDD=1.8 V. The output voltage errors, which the main cause is due to input voltage variations, even when the circuit is in latch mode, are analyzed in this paper. The post-layout results, using a clock frequency at 10 GHz, and the same bias current of 6 mA for both circuits shows an increment of 60 % for the output voltage swing in the proposed latch versus the typical latch. Besides, this topology being more robust it can be used for higher frequencies up to 20 GHz. more...

This paper aims to design a low-power and high-frequency divider in an integrated CMOS phase-locked loop. The proposed frequency divider is a two-step divider composed of an injection-locked frequency divider (ILFD) and a current-mode logic (CML) frequency divider. The ILFD has a structure similar to an LC cross-coupled oscillator to adjust the frequency alignment between the oscillator and the ILFD. The LC cross-coupled oscillator operates at 50 GHz, and the ILFD is supposed to provide a divide-by-2 (/2) operation. The CML frequency divider, which is used as the second-stage divider, is applied with an inductive peaking structure for a wide band with low power consumption. The proposed two-step frequency divider is designed with a 0.18 µm CMOS process. By varying the numbers of the ILFD and the CML divider, the characteristics of power consumption are also studied. Post-layout simulation shows that the /2 ILFD and the /128 CML frequency divider operate at an input frequency of 50 GHz, with power consumption of 37.8 mW, and results indicate a low-power two-step divider at high frequency. more...

This paper presents a new topology to implement MOS current mode logic (MCML) tri-state buffer. The current source section of the available MCML tri-state buffer is modified in the proposed topology which improves output enable time and maintains the low power feature. The functionality of the proposed topology is verified through SPICE simulations by using 0.18 µm TSMC CMOS technology parameters. Its performance is compared with the available one for different values of bias current ranging from 50 to 200 µA. The delay decreases with increase in current and improvement in output enable time is visible throughout the current range. The impact of parameter variations at different design corners and width mismatch on the performance of both the proposed and the available tri-state buffers is also studied and similar variations are found. The significance of the improvement is demonstrated through the implementation of a tri-state buffer based edge triggered register, a key element in digital systems design. more...

A quarter-rate 4-tap decision feedback equalizer (DFE) using new analog sampling and soft-decision technique is proposed in this paper. The proposed DFE introduces two optimizations on basis of the original soft-decision DFE. Firstly, implementation of sample-and-hold circuit is changed into the cascade transmission gates to simplify the clock generation. Secondly, 4-tap structure is realized without increasing any hardware complexity to enhance the ability of equalization. To verify the DFE, a simplified transceiver is designed and fabricated in UMC 0.18-μm CMOS process, which mainly consists of a 4-tap DFE, a clock receiver and generator and a 4 to 1 multiplexer. The measurement results show that the quarter-rate 4-tap DFE can equalize 9 Gb/s 27?1 PRBS data passed over a 20 cm FR-4 channel with 16.3 dB of loss at 4.5 GHz and achieve 0.46UI timing margin for bit error rate = 10?12. The active area of the whole transceiver is 0.65 ? 0.24 mm2, while the DFE occupies 0.13 ? 0.18 mm2 and draws 7.2 mA from 1.8 V supply. more...

This paper presents a low phase noise integer-N phase-locked loop (PLL) for V-band signal generation. To enhance the frequency stability, we use a new class of Vackar voltage-controlled oscillator (VCO) in the PLL. The Vackar VCO achieves a low phase noise performance by effectively suppressing the AM-PM conversion. To properly align the locking range with the output of the VCO, a divider with wide locking range is realized by the current-mode logic (CML) D-flip-flops with tunable load. For spur reduction, an enhanced charge-pump structure is used to reject transient current glitches. With good static and dynamic current matching achieved in the charge pump, the reference spur is suppressed down to ?50 dBc. The designed PLL is implemented in a 65 nm RFCMOS process, and the measurement demonstrates a low phase noise signal up to 17 GHz. The in-band phase noise (at 1 MHz offset) and out-band phase noise (at 50 MHz offset) are ?103.6 and ?126.8 dBc/Hz, respectively. The PLL consumes 50.7 mW and occupies a chip area of 0.9 mm2. more...

In this paper, a low-power tri-state buffer in MOS current mode logic (MCML) is proposed. It offers power saving by reducing the overall current flow in the circuit during the high-impedance state. The proposed MCML tri-state buffer is simulated in PSPICE using 0.18 μm TSMC CMOS technology parameters. Its performance comparison with the existing MCML tri-state buffers indicates that the proposed tri-state buffer is power efficient than the others. more...

A wired-AND current-mode logic (WCML) circuit technique in CMOS technology for low-voltage and high-speed VLSI circuits is proposed, and a WCML cell library is developed using standard 0.8 micron CMOS process. The proposed WCML technique applies the analog circuit design methodologies to the digital circuit design. The input and output logic signals are represented by current quantities. The supply current of the logic circuit is adjustable for the required logic speed and the switching noise level. The noise is reduced on the power supply lines and in the substrate by the current-steering technique and by the smooth swing of the reduced node potentials. Precise analog circuits and fast digital circuits can be integrated on the same silicon substrate by using the low noise property of the WCML. It is shown by the simulations that at low supply voltages, the WCML is faster and generates less switching noise when compared to the static-CMOS logic. At high speeds, the power dissipation of the WCML is less than that of the static-CMOS logic. more...