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A novel CMOS transistor implementation of three stage amplifier is presented in this work. The floating gate metal oxide semiconductor (FGMOS) transistor current mirror is exploited here to minimize supply requirements and to overcome the bandwidth reduction due to FGMOS transistor, frequency compensation techniques have been applied in subsequent stages. This amplifier is useful for application of low-voltage low-power VLSI as it requires a dual supply of only ± 0.5 V. The power consumption is 0.157 mW and slew rate is 6.5 V/μs. The gain bandwidth product of the circuit is calculated as 59.1 MHz and dc gain is 111.5 dB. All simulations are carried out in 180 nm technology with spice tools.

Proposed in this paper is design and analysis of an enhanced recycling folded cascode (RFC) Op-Amp. This structure is achieved using connecting two nodes and eliminating some devices in the conventional RFC. This effect enhances the DC gain with increasing output resistance of differential pair compared to the conventional RFC circuit. In the same − 3 dB frequency, the unity gain bandwidth is also increased. Moreover, for the same slew rate and input referred noise performance, other proposed improvements are the fast-settling time and total harmonic distortion. Hspice simulation results in 90 nm CMOS standard technology demonstrate that the proposed amplifier has 1.2 times the unity gain bandwidth (190 vs. 160 MHz) and also has twice gain boosting (66.2 vs. 59.5 dB) in the same − 3 dB frequency, power supply (1.2 V) and driving capacitor load of 5 pF.

A new method to compensate three-stage amplifier to drive large capacitive loads is proposed in this paper. Gain Bandwidth Product is increased due to use an attenuator in the path of miller compensation capacitor. Analysis demonstrates that the gain bandwidth product will be improved significantly without using large compensation capacitor. Using a feedforward path is deployed to control a left half plane zero which is able to cancel out first non-dominant pole. A three stage amplifier is simulated in a 0.18 μm CMOS technology. The purpose of the design is to compensate three-stage amplifier loading 1000 pF capacitive load. The simulated amplifier with a 1000 pF capacitive load is performed in 3.3 MHz gain bandwidth product, and phase margin of 50. The compensation capacitor is reduced extremely compared to conventional nested miller compensation methods. Since transconductance of each stage is not distinct, and it is close to one another; as a result, this method is suitable low power design methodology.

A two-stage, fully differential amplifier is presented in this work. The proposed amplifier enjoys from an intrinsic common-mode feedback scheme, which eliminates the extra common-mode circuitries that are essential in typical fully differential circuits. Besides, the proposed architecture introduces a left-half-plane zero which can be adjusted to cancel out the dominant pole and thus to extend the structure's bandwidth. The simulation results with TSMC 180 nm standard CMOS technology shows the 92.2 dB DC gain and 49 MHz gain bandwidth product with 89° of phase margin. The amplifier consumes 0.45 mW from 1.8 V power supply.

This paper presents two high-gain amplifiers fabricated in a flexible self-aligned amorphous indium gallium zinc oxide thin-film transistor (TFT) technology. One common-source amplifier relies on positive feedback to provide a voltage gain of 17 dB, and a bandwidth of 79 kHz from a dc power of only 0.76 mW. One cascode amplifier provides a voltage gain of 25 dB, and a bandwidth of 220 kHz from a dc power of 2.32 mW. The chip areas of the amplifiers are 7.5 and 10.3 mm2, respectively. By using a gain-enhancement technique in the first amplifier, gain, dc power consumption, and chip area are greatly improved. The presented amplifiers are designed for using as audio pre-amplifiers in a radio receiver. The presented measurements confirm that the amplifiers meet the requirements for this purpose. The circuits are designed using the Verilog-A Rensselaer Polytechnic Institute-amorphous TFT model; circuit simulations are also presented for comparison with the hardware characterization. Additionally, the impact of process variations on the amplifiers is analyzed and discussed in details.

Recently introduced MOS-FGMOS split length cell has been used to increase the DC gain of a fully differential op amp. Resultant proposed opamp structure exhibits gain of 97 dB and unity gain bandwidth of 400 MHz with power consumption of 1.2 mW. An opamp design has been verified with Cadence Spectre using a 130 nm technology at 1.2 V and has a slew rate of $$53\,\hbox {V}/\mu \hbox {s}$$ 53 V / μ s with a phase margin of $$78^{\circ }$$ 78 ? .

This paper proposes a novel tailless ultra low power low voltage high CMRR differential amplifier (D.A.) with rail-to-rail input common mode range (ICMR) based on quasi floating gate (QFG) transistors. For low voltage operation, the tail current source of the conventional D.A. is removed and the resulted lack of CMRR is highly compensated by means of two simple inverters. The required supply voltage is only VGS + VDSsat (with their usual meanings of symbols) which is one VDSsat lower than the required supply voltage for the conventional D.A. Unlike the conventional differential amplifier, slew rate (SR) in the proposed one is not limited by the tail current source and is determined by the amplitude of input signals. The principle of operation, small signal analysis and the formula of the most important parameters of the proposed D.A. are presented. HSPICE simulation results using TSMC 0.18 μm CMOS process parameters and ±0.4 V supply voltage are presented which verify the high performance of the proposed scheme. The simulation results show a rail-to-rail operation and 121 dB CMRR for the proposed tailless differential amplifier. The corner case simulation results are also provided which show a robust performance for the proposed structure. Its unity gain bandwidth product is 72.3 MHz that is 2.31 times larger than that of conventional differential amplifier. Positive and negative SRs are improved by a factor of 7.4 and 3.58 times respectively compared to conventional one. It has also an ultra low power dissipation of 6.89 μW.

This paper concerns the design, the implementation and the validation of a fully integrated front-end receiver for a portable ultrasonic system. This front-end receiver includes a logarithmic preamplification circuit and followed by a programmable-gain compensator. The proposed building blocks largely amplify small amplitude signals, and moderately the large amplitude ones. They also compensate signal attenuation due to its traveling of several human body tissues. The ultrasonic receiver is implemented in CMOS 0.35 μm technology. Spectre simulations of the front-end receiver show unity gain bandwidth higher than 100 MHz when driving a load of 1 pF. The expected measurements of the fabricated chip are reported. This chip operates at 3.3 V supply voltages, while maintaining wide common mode rejection ratio, high gain and low input offset voltage. The total power consumption is 15.6 mW and the total chip area is 7.2 mm2 including the digital part needed to program the TGC.

Two variants of a new current feedback amplifier (CFA) are presented in this paper. These CFAs are realized in CMOS technology and both are capable of working at low voltages. It is shown that one circuit performs better than the other by virtue of an increased impedance at its i>Z terminal achieved through the use of additional transistors. Analysis of both variants of the current conveyor and buffer that form the current feedback amplifier gives an insight into the location of primary poles and zeros of the CFAs. Simulation results indicate an overall gain bandwidth product in excess of 59 MHz and 102 MHz for each circuit at a gain of −10 and with a 3.3 V supply. Experimental results from a chip fabricated in a 0.35 μm CMOS technology agree closely with the simulation results.