1. A low noise 0.9 GHz FBAR clock
- Author
-
Miikka Ylimaula, Markku Ylilammi, Arto Rantala, Markku Åberg, and Tuomas Pensala
- Subjects
Engineering ,business.industry ,Clock signal ,Pipeline (computing) ,Electrical engineering ,Hardware_PERFORMANCEANDRELIABILITY ,Surfaces, Coatings and Films ,Low noise ,Hardware and Architecture ,Signal Processing ,Phase noise ,Hardware_INTEGRATEDCIRCUITS ,Electronic engineering ,business ,Cmos process ,Temperature coefficient ,Jitter - Abstract
A low noise 0.9 GHz FBAR clock consisting of an oscillator and divider circuit for single-sided-to-differential conversion for a high-speed interleaved pipeline A/D-converter was designed, realized with an in-house FBAR and a commercial 0.35 ?m CMOS process, and tested. The circuit showed very good jitter and phase noise performance. A temperature coefficient of ---47 ppm/K was measured.
- Published
- 2007