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The effects of incorporating Al into HfO2 as gate dielectric on the back-gated MoS2 transistor are investigated. Hf0.5Al0.5O as gate dielectric exhibits excellent electrical characteristics: on/off ratio of 1.8 × 107, carrier mobility of 49.3 cm2/(V s), subthreshold swing of 118 mV dec−1, interface-state density of 2.3 × 1012 eV−1 cm−2, due to the Al incorporation into the HfO2 can passivate the defective states induced by oxygen vacancies and improve the dielectric densification and uniformity to obtain an excellent MoS2/Hf1-x Al x O interface. Besides, the intrinsic carrier mobility of 100 cm2 V−1 s−1 and contact resistance of 11.1 kΩ/μm indicates that the contact resistance is a main factor limiting the mobility.

Atomic layer deposited HfO2 annealed in different ambients (N2, O2, and NH3) is used to replace SiO2 as a gate dielectric for fabricating back-gated multilayer MoS2 transistors. Excellent electrical properties such as a mobility of 15.1 cm2/(V·s), an on/off ratio exceeding 107, and a hysteresis of 0.133 V are achieved for samples annealed in NH3 at 400 °C for 10 min. This is caused by the NH3 annealing passivation effects that reduce defective states in the HfO2 dielectric and the interface. The capacitance equivalent thickness is only 7.85 nm, which is quite small for a back-gated MoS2 transistor and is conducive to the scaling down of the device.

GaAs metal–oxide–semiconductor (MOS) capacitors with HfTiON as a gate dielectric and Ga2O3(Gd2O3) (GGO) as an interlayer annealed in NH3 or N2 are fabricated, and their electrical properties are characterized. Experimental results show that the HfTiON/GGO/GaAs MOS device annealed in NH3 exhibits a low interface-state density (1.1 × 1012 cm−2 eV−1), a small gate leakage current (1.66 × 10−4 A cm−2 at Vg = Vfb + 1 V), a large equivalent dielectric constant (25.7), and a good capacitance–voltage behavior. All these should be attributed to the fact that the GGO interlayer and postdeposition annealing in NH3 can effectively suppress the formation of interfacial Ga/As oxides and remove the excess As atoms at the GaAs surface, thus reducing the relevant defects at/near the GGO/GaAs interface.

The properties of ZrO2 and ZrON as the charge-trapping layer (CTL) of metal–oxide–nitride–oxide–silicon memory are investigated. The microstructure and chemical bonding are examined by X-ray diffraction and X-ray photoelectron spectroscopy. It is found that nitrogen incorporation in ZrO2 can induce more charge-trapping sites, effectively suppress the formation of zirconium silicate (leading to better interface quality between the CTL and the SiO2 tunneling layer), and increase the dielectric constant of ZrO2, thus improving the memory performances (large memory window, high program/erase speed, good endurance characteristics, and small charge loss).