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Graphene field effect transistors and capacitors that employ ultra-thin atomic layer deposited high-κ TiO2 dielectrics are demonstrated. Of the three TiO2 gate insulation schemes employed, the sequentially deposited HfO2:TiO2 gate insulator stack enabled the reduction of equivalent oxide thickness while simultaneously providing an ultra-thin gate insulation layer that minimized gate leakage current. The multilayer gate insulation scheme demonstrates a means for advanced device scaling in graphene-based devices. [ABSTRACT FROM AUTHOR]

SnSe2 field-effect transistors fabricated using mechanical exfoliation are reported. Substrate-gated devices with source-to-drain spacing of 0.5 μm have been fabricated with drive current of 160 μA/μm at T = 300 K. The transconductance at a drain-to-source voltage of Vds = 2 V increases from 0.94 μS/μm at 300 K to 4.0 μS/μm at 4.4 K, while the field-effect mobility increases from 8.6 cm2/Vs at 300 K to 28 cm2/Vs at 77 K. The conductance at Vds = 50 mV shows an activation energy of only 5.5 meV, indicating the absence of a significant Schottky barrier at the source and drain contacts. [ABSTRACT FROM AUTHOR]