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CuO grown by room-temperature direct current reactive magnetron sputtering is introduced to realize p-type thin-film transistors (TFTs) with a high-k HfO2 gate dielectric fabricated by atomic layer deposition. The devices work in an accumulation mode (AM) with two apparent threshold voltages corresponding to the formation of a buried channel and an accumulation layer, respectively. A CuO AM TFT with a channel length of 25 μm exhibit a competitive on-off ratio (Ion/Ioff) of 1.3 × 102, a subthreshold swing (SS) of 1.04 V dec−1, and a field-effect mobility (μFE) of 1.1 × 10−3 cm2 V−1 s−1 at room temperature. By measuring a CuO metal oxide semiconductor (MOS) capacitor at room temperature, a high acceptor doping density (NA) of ∼5 × 1017 cm−3, a high positive effective fixed surface charge density (Qf) of ∼9 × 1012 cm−2, and a low interfacial trap charge density (Dit) of ∼6 × 1010 eV−1 cm−2 at the HfO2/CuO interface are estimated. The μFE extracted from the accumulation regime appears lower than the Hall mobility measured for a similarly processed CuO layer on glass due to the increased hole concentration in CuO TFTs, compared to a Hall concentration of ∼1014 cm−3, following the MOS process. SS appears limited by the decreased channel to gate capacitance (Ccg) related to the buried channel in AM TFTs, parasitic capacitance to ground, and potentially very high interfacial traps at the non-passivated CuO/air interface. [ABSTRACT FROM AUTHOR]

In this paper, negative transconductance (NTC) behavior in molybdenum disulfides (MoS2) field effect transistors (FETs) is investigated. Combining experimental observation and numerical analysis, we demonstrate that positive shift in the device transfer curves results from the electron trapping/de-trapping processes, where the defect densities at the MoS2/SiO2 interface are reduced when the temperature T decreases from 300 to 200 K. Moreover, the main types of defects that affect the device electrical performance are the interface defect and bulk sulfur vacancy VS in which VS induces the p-type doping effect. While decreasing T below 100 K, NTC occurs when their active layer thickness t (=41 and 35 nm) is larger than the Debye length λ (28 nm). Considering the n-type doping effect induced by the interface defects and the p-type doping caused by the bulk S vacancies, these two opposite doping regions are carefully implemented in simulation at T = 70 K. A vertical barrier induced by the inhomogeneous electron distribution enlarges with the increased gate bias VGS and, thereafter, leads to the unconventional increase in the contact and total resistances with t > λ. While t ≦ λ, the barrier and NTC behavior disappear. The current IDS and transconductance g obtained from the simulation confirm the low-temperature NTC mechanism related to the defects as discussed above. The material defects and physical origin of NTC discussed in the multilayer MoS2 transistors provide the theoretical foundation for designing and realizing novel structures of functional devices via defect engineering in the two-dimensional FET. [ABSTRACT FROM AUTHOR]

CuO grown by room-temperature direct current reactive magnetron sputtering is introduced to realize p-type thin-film transistors (TFTs) with a high-k HfO2 gate dielectric fabricated by atomic layer deposition. The devices work in an accumulation mode (AM) with two apparent threshold voltages corresponding to the formation of a buried channel and an accumulation layer, respectively. A CuO AM TFT with a channel length of 25 μm exhibit a competitive on-off ratio (Ion/Ioff) of 1.3 × 102, a subthreshold swing (SS) of 1.04 V dec−1, and a field-effect mobility (μFE) of 1.1 × 10−3 cm2 V−1 s−1 at room temperature. By measuring a CuO metal oxide semiconductor (MOS) capacitor at room temperature, a high acceptor doping density (NA) of ∼5 × 1017 cm−3, a high positive effective fixed surface charge density (Qf) of ∼9 × 1012 cm−2, and a low interfacial trap charge density (Dit) of ∼6 × 1010 eV−1 cm−2 at the HfO2/CuO interface are estimated. The μFE extracted from the accumulation regime appears lower than the Hall mobility measured for a similarly processed CuO layer on glass due to the increased hole concentration in CuO TFTs, compared to a Hall concentration of ∼1014 cm−3, following the MOS process. SS appears limited by the decreased channel to gate capacitance (Ccg) related to the buried channel in AM TFTs, parasitic capacitance to ground, and potentially very high interfacial traps at the non-passivated CuO/air interface. [ABSTRACT FROM AUTHOR]