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We investigated the deep-level traps formed in Cr-SrTiO3/Si3N4/SiO2 structures deposited on n-type Si by deep-level transient spectroscopy (DLTS). Three electron traps, with averaged activation energies of 0.24, 0.28, and 0.53 eV, were observed below the conduction band minimum of Si. Different behaviors in the dependence of DLTS on both filling bias and pulse confirm that the traps originate as the Si3N4 bulk trap, the Si3N4/SiO2 interfacial trap, and the Si/SiO2 interfacial trap. We also demonstrate that a specific point defect is the source of memory behavior in Cr-SrTiO3-based fusion-type charge trap flash (CTF) memory devices.

In this paper, we propose a charge-trap flash memory device using a ferroelectric material, Sr0.7Bi2.3Nb2O9 (SBN), with spontaneous polarization as a blocking layer. This device consists of metal/SBN/nitride/oxide/silicon and has an advantage in the carrier injection into the nitride from the silicon due to polarization charges formed in the ferroelectric material. Compared to conventional metal/oxide/nitride/oxide/silicon memory devices, the proposed devices showed a larger memory window (7 V), faster program/erase (P/E) speeds (100/500 μs), and higher endurance (105 P/E cycles) with comparable retention properties.

We examined the origin of the charge traps in bothSiO2/Si3N4/SiO2 (ONO) and Al2O3/Si3N4/SiO2 (ANO) structures and their effect on the memory characteristics by capacitance-voltage (C-V) measurements and deep level transient spectroscopy (DLTS). A larger memory window was observed by C-V for ANO, due to its higher trap density. The DLTS showed that nitride traps are dominant in ANO, while more Si/SiO2 interface-related traps are observed in ONO. The ANO capacitor outperforms the ONO one in terms of both the program efficiency and retention, which is attributed to the reduced number of interface traps in ANO.

The origin of the electron memory trap in an oxide-nitride-oxide structure deposited on n-type Si is investigated by both capacitance-voltage and deep level transient spectroscopy (DLTS). Two electron traps are observed near 0.27 and 0.54eV, below the conduction band minimum of Si and are identified as the nitride bulk trap and the Si–SiO2 interfacial trap, respectively. The trap depth, viz., vertical distribution of the electron trap, in both nitride bulk and Si–SiO2 interface, are also estimated from the bias voltage dependent DLTS.