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In this study, a three-level static RAM cell with a single BL based on 16 nm BWG CNFET technology is proposed for use in high-performance IoT platforms. The proposed memory structure in a bit-interleaved architecture compatible design consists of a standard triple buffer gate (STB) based on the BWG CN-TGDI method and a pair of transmission gates as an access network. In the STB cell structure, the threshold voltage calibration by the flat band voltage parameter of the CNTs has been used to improve the static noise margin at logic level '1'. In addition, pseudo-resistor and stacked transistor structures have been used to control the single static current path during logic level '1' generation and cell leakage current, respectively. The simulation results based on the Monte Carlo method show that the hardware performance parameters PDP and EDP for the proposed design have been improved by 38.8% and 31%, respectively, compared to the counterpart structure. Moreover, the proposed architecture has shown a more reasonable result in terms of noise immunity than the best-performing design by 1.93 times. Finally, to investigate a real-world application, the triple memory structure has been used to store the colored QR code image with the data content of three values using the proposed hardware algorithm. The obtained results for the quality evaluation metrics, PSNR and MSSIM, emphasize the suitability of the proposed memory architecture for the development of next-generation SoCs. [ABSTRACT FROM AUTHOR]